Datasheet.kr


3010 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 3010
기능 Memory Controller Hub
제조업체 Intel
로고 ( 디자인 ) Intel 로고 
미리보기

( 핀배열 )


전체 30 페이지

		
3010 데이터시트 및 3010 PDF

1페이지

3010 pdf, 반도체, 판매, 대치품
4.1.14 PCIEXBAR—PCI Express Register Range Base Address (D0:F0) .....................53
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) .....................55
4.1.16 DEVEN—Device Enable (D0:F0) ................................................................56
4.1.17 DEAP - DRAM Error Address Pointer (D0:F0)...............................................56
4.1.18 DERRSYN - DRAM Error Syndrome (D0:F0) ................................................57
4.1.19 DERRDST - DRAM Error Destination (D0:F0)...............................................57
4.1.20 PAM0—Programmable Attribute Map 0 (D0:F0) ...........................................58
4.1.21 PAM1—Programmable Attribute Map 1 (D0:F0) ...........................................59
4.1.22 PAM2—Programmable Attribute Map 2 (D0:F0) ...........................................59
4.1.23 PAM3—Programmable Attribute Map 3 (D0:F0) ...........................................60
4.1.24 PAM4—Programmable Attribute Map 4 (D0:F0) ...........................................60
4.1.25 PAM5—Programmable Attribute Map 5 (D0:F0) ...........................................61
4.1.26 PAM6—Programmable Attribute Map 6 (D0:F0) ...........................................61
4.1.27 LAC—Legacy Access Control (D0:F0) .........................................................62
4.1.28 REMAPBASE - Remap Base Address Register ..............................................63
4.1.29 REMAPLIMIT - Remap Limit Address Register..............................................63
4.1.30 TOLUD—Top of Low Usable DRAM (D0:F0) .................................................64
4.1.31 SMRAM—System Management RAM Control (D0:F0)....................................64
4.1.32 ESMRAMC—Extended System Management RAM Control (D0:F0) ..................65
4.1.33 TOM - Top of Memory..............................................................................66
4.1.34 ERRSTS—Error Status (D0:F0) .................................................................67
4.1.35 ERRCMD—Error Command (D0:F0) ...........................................................68
4.1.36 SMICMD - SMI Command (D0:F0).............................................................69
4.1.37 SCICMD - SCI Command (D0:F0) .............................................................69
4.1.38 SKPD—Scratchpad Data (D0:F0)...............................................................70
4.1.39 CAPID0—Capability Identifier (D0:F0) .......................................................70
4.1.40 EDEAP—Extended DRAM Error Address Pointer (D0:F0) ...............................70
4.2 MCHBAR Configuration Register Details.................................................................71
4.2.1 C0DRB0—Channel A DRAM Rank Boundary Address 0..................................72
4.2.2 C0DRB1—Channel A DRAM Rank Boundary Address 1..................................73
4.2.3 C0DRB2—Channel A DRAM Rank Boundary Address 2..................................73
4.2.4 C0DRB3—Channel A DRAM Rank Boundary Address 3..................................73
4.2.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute ............................................74
4.2.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute ............................................74
4.2.7 C0DCLKDIS—Channel A DRAM Clock Disable ..............................................75
4.2.8 C0BNKARC—Channel A DRAM Bank Architecture .........................................76
4.2.9 C0DRT1—Channel A DRAM Timing Register ...............................................76
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 .............................................77
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 .............................................78
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0..................................79
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1..................................79
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2..................................79
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3..................................79
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................................79
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................................79
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ..............................................80
4.2.19 C1BNKARC—Channel B Bank Architecture ..................................................80
4.2.20 C1DRT1—Channel 1 DRAM Timing Register 1 .............................................80
4.2.21 C1DRC0—Channel 1 DRAM Controller Mode 0 .............................................80
4.2.22 C1DRC1—Channel 1 DRAM Controller Mode 1 .............................................80
4.2.23 PMCFG—Power Management Configuration.................................................81
4.2.24 PMSTS—Power Management Status...........................................................81
4.3 Egress Port Register Summary ............................................................................82
4.3.1 EPESD—EP Element Self Description..........................................................83
4.3.2 EPLE1D—EP Link Entry 1 Description .........................................................83
4.3.3 EPLE1A—EP Link Entry 1 Address..............................................................84
4 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet

4페이지

3010 전자부품, 판매, 대치품
8.3.2 HSEG (FEDA_0000h-FEDB_FFFFh) .......................................................... 153
8.3.3 FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF) .............................. 153
8.3.4 High BIOS Area.................................................................................... 153
8.4 Main Memory Address Space (4 GB to Remaplimit) .............................................. 153
8.4.1 Top of Memory..................................................................................... 153
8.4.2 Memory Re-claim Background ................................................................ 154
8.4.3 Memory Re-mapping............................................................................. 154
8.4.4 PCI Express Configuration Address Space ................................................ 154
8.4.5 PCI Express ......................................................................................... 155
8.5 System Management Mode (SMM) ..................................................................... 155
8.5.1 SMM Space Definition ........................................................................... 156
8.5.2 SMM Space Restrictions ........................................................................ 156
8.5.3 SMM Space Combinations ...................................................................... 156
8.5.4 SMM Control Combinations .................................................................... 157
8.5.5 SMM Space Decode and Transaction Handling .......................................... 157
8.5.6 CPU WB Transaction to an Enabled SMM Address Space............................. 157
8.5.7 Memory Shadowing .............................................................................. 157
8.5.8 I/O Address Space................................................................................ 157
8.5.9 PCI Express I/O Address Mapping ........................................................... 158
8.5.10 MCH Decode Rules and Cross-Bridge Address Mapping .............................. 158
8.5.11 Legacy VGA and I/O Range Decode Rules ................................................ 158
9 Functional Description ............................................................................................... 159
9.1 Host Interface................................................................................................. 159
9.1.1 FSB IOQ Depth .................................................................................... 159
9.1.2 FSB OOQ Depth ................................................................................... 159
9.1.3 FSB GTL+ Termination .......................................................................... 159
9.1.4 FSB Dynamic Bus Inversion ................................................................... 159
9.2 System Memory Controller ............................................................................... 160
9.2.1 System Memory Configuration Registers Overview .................................... 161
9.2.2 DRAM Technologies and Organization...................................................... 162
9.2.3 DRAM Clock Generation......................................................................... 164
9.2.4 DDR2 On Die Terminations .................................................................... 164
9.3 PCI Express .................................................................................................... 165
9.3.1 PCI Express Architecture ....................................................................... 165
9.3.2 Configurations (Intel® 3010 chipset only) ............................................... 165
9.3.3 Lane Reversal ...................................................................................... 167
9.3.4 PCI Express Straps (Intel® 3010 chipset only) ......................................... 168
9.3.5 Peer-to-Peer ........................................................................................ 169
9.3.6 Peer-to-Peer Latency ............................................................................ 170
9.3.7 PCI Express Error Flow .......................................................................... 171
9.3.8 PCI Express Interrupt and GPE Flow........................................................ 172
9.4 Power Management ......................................................................................... 172
9.5 Clocking......................................................................................................... 172
10 Electrical Characteristics ............................................................................................ 173
10.1 Absolute Minimum and Maximum Ratings ........................................................... 173
10.2 Power Characteristics....................................................................................... 174
10.3 Signal Groups ................................................................................................. 175
10.4 DC Characteristics ........................................................................................... 177
11 Ballout and Package Information ................................................................................ 179
11.1 Ballout ........................................................................................................... 179
11.2 MCH Ballout Table ........................................................................................... 182
11.3 Package ......................................................................................................... 202
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
7

7페이지





구       성총 30 페이지
다운로드[ 3010.PDF 데이터시트 ]
구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-------------------------------------------------------------------------------------------

전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 ) : 010-3582-2743

상호 : 아이지 인터내셔날, 전화번호 : 051-319-2877, [ 홈페이지 ]



링크공유

링크 :

관련 데이터시트

부품번호상세설명 및 기능제조사
3010

The functions of this components is a Memory Controller Hub.

Intel
Intel
3010KM

The functions of this components is a SI-3010KM.

Allegro MicroSystems
Allegro MicroSystems
30129-13

The functions of this components is a Geode GXLV Processor Series Low Power Integrated x86 Solutions.

National Semiconductor
National Semiconductor
30130-23

The functions of this components is a Geode GXm Processor Integrated x86 Solution with MMX Support.

National Semiconductor
National Semiconductor
30131-23

The functions of this components is a Geode GXm Processor Integrated x86 Solution with MMX Support.

National Semiconductor
National Semiconductor

추천 데이터시트

부품번호상세설명 및 기능제조사
2P4M

이 부품은 2A, 400V, P gate all diffused mold type Thyristor 입니다. The 2P4M and 2P6M are a P gate all diffused mold type Thyristor granted 2 A On-state Average Current (TC = 77°C), with rated voltages up to 600 V.

NEC
NEC
CQ1565RT

FSCQ1565RT, Green Mode Fairchild Power Switch. In general, a Quasi-Resonant Converter (QRC) shows lower EMI and higher power conversion efficiency compared to conventional hard-switched converter with a fixed switching frequency.

Fairchild
Fairchild
KF16N25D

MOSFET의 기능은 N Channel MOS Field effect transistor입니다. This planar stripe MOSFET has better characteristics, such as fast switching time, low on resistance, low gate charge and excellent avalanche characteristics. It is mainly suitable for DC/DC Converters and switching mode power supplies.( Vdss=250V, Id=13A )

KEC
KEC
FR9884

컨버터의 기능은 340KHz Synchronous Step-Down DC/DC Converter 입니다. The FR9884 is a synchronous step-down DC/DC converter that provides wide 4.5V to 18V input voltage range and 3A continuous load current capability.

Fitipower
Fitipower

www.DataSheet.kr    |   2018   |  연락처   |  링크모음   |   검색  |   사이트맵