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부품번호 | NTY100N10 기능 |
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기능 | Power MOSFET ( Transistor ) | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 8 페이지수
NTY100N10
Preferred Device
Power MOSFET 123 A,
100 V N−Channel
Enhancement−Mode TO264
Package
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
• Pb−Free Package is Available*
Applications
• PWM Motor Control
• Power Supplies
• Converters
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−Source Voltage
Drain−Gate Voltage (RGS = 1 MW)
Gate−Source Voltage
− Continuous
− Non−Repetitive (tp v 10 ms)
Drain Current (Note 1)
− Continuous @ TC = 25°C
− Pulsed
Total Power Dissipation (Note 1)
Derate above 25°C
VDSS
VDGR
100
100
V
V
VGS
VGSM
ID
IDM
PD
$ 20
$ 40
123
369
313
2.5
V
V
A
A
Watts
W/°C
Operating and Storage Temperature Range
TJ, Tstg −55 to
150
°C
Single Pulse Drain−to−Source
Avalanche Energy − Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc,
Peak IL = 100 Apk, L = 0.1 mH, RG = 25 W)
Thermal Resistance
− Junction to Case
− Junction to Ambient
Maximum Lead Temperature for Soldering
Purposes, 0.125 in from case for 10 seconds
EAS
RRqqJJCA
TL
500 mJ
0.4 °C/W
25
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty−Cycle = 2%.
http://onsemi.com
123 A, 100 V
9 mW @ VGS = 10 V (Typ)
N−Channel
D
G
S
MARKING DIAGRAM &
PIN ASSIGNMENT
12 3
TO−264
CASE 340G
STYLE 1
NTY100N10
AYYWWG
123
GDS
A = Assembly Location
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
NTY100N10
NTY100N10G
Package
TO−264
TO−264
(Pb−Free)
Shipping
25 Units/Rail
25 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1
Publication Order Number:
NTY100N10/D
NTY100N10
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to
VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but
since di/dt is a function of drain current, the mathematical
solution is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive
load, which approximates an optimally snubbed inductive
load. Power MOSFETs may be safely operated into an
inductive load; however, snubbing reduces switching
losses.
http://onsemi.com
4
4페이지 NTY100N10
SAFE OPERATING AREA
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E−05
1.0E−04
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 13. Thermal Response
1.0E+00
1.0E+01
di/
IS dt
trr
ta tb
TIME
tp 0.25 IS
IS
Figure 14. Diode Reverse Recovery Waveform
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7
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부품번호 | 상세설명 및 기능 | 제조사 |
NTY100N10 | Power MOSFET ( Transistor ) | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |