PDF 78P2352 Data sheet ( Hoja de datos )

Número de pieza	78P2352
Descripción	Dual Channel OC-3/ STM1-E/ E4 LIU
Fabricantes	Teridian Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de 78P2352 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! DESCRIPTION The 78P2352 is Teridian’s second generation Line Interface Unit (LIU) for 155 Mbps SDH/SONET (OC-3, STS-3, or STM-1) and 140 Mbps PDH (E4) telecom interfaces. The device is a dual channel, single chip solution that includes an integrated CDR in the transmit path for flexible NRZ to CMI conversion. The device can interface to 75Ω coaxial cable using CMI coding or directly to a fiber optics transceiver module using NRZ coding. The 78P2352 is compliant with all respective ANSI, ITU- T, and Telcordia standards for jitter tolerance, generation, and transfer. APPLICATIONS • Central Office Interconnects • DSLAMs • Add Drop Multiplexers (ADMs) • Multi Service Switches • Digital Microwave Radios 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU DATA SHEET SEPTEMBER 2006 FEATURES • ITU-T G.703 compliant cable driver for 139.264 Mbps or 155.52 Mbps CMI-coded coax transmission • Integrated adaptive CMI equalizer and CDR in receive path handles over 12.7dB of cable loss • Serial, LVPECL system interface with integrated CRU in transmit path for flexible NRZ to CMI conversion. • 4-bit parallel CMOS system interface with master and slave Tx clock modes. • Selectable LVPECL compatible NRZ media interface for 155.52 Mbps optical transmission. • Configurable via HW control pins or 4-wire serial port interface • Compliant with ANSI T1.105.03-1994; ITU-T G.751, G.813, G.823, G.825, G.958; and Telcordia GR-253-CORE for jitter performance. • Receiver Loss of Signal (LOS) detection compatible with ITU-T G.783 • Operates from a single 3.3V supply • Standard and thermally enhanced 128-pin JEDEC LQFP package options BLOCK DIAGRAM SIxDP/N SIxCKP/N PIxCK PIx[3:0]D PTOxCK Lock Detect Tx CDR EACH CHANNEL: Tx FIFO CMI Encoder PMOD, SMOD[1:0], PAR RLBK ECLxP/N TXxCKP/N CMIxP/N SOxCKP/N SOxDP/N POx[3:0]D POxCK CMI Decoder Rx CDR Lock Detect CMI EACH CHANNEL: Rx Adaptive Eq. LOS Detect LLBK RXxP/N Page: 1 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 1 page Receive Loss of Signal The 78P2352 includes a Loss of Signal (LOS) detector. When the peak value of the received CMI signal is less than approximately 19dB below nominal for approximately 110 UI, Receive Loss of Signal is asserted. The Rx LOS signal is cleared when the received signal is greater than approximately 18dB below nominal for 110 UI. In ECL mode, the LOSx signal will be asserted when there are no transitions for longer than 2.3µs. The signal is cleared when there are more than 4 transitions in 32 UI. It is generally recommended to use the LOS status signal from the optical transceiver module. During Rx LOS conditions, the receive clock will remain on the last selected phase tap of the Rx DLL outputting a stable clock while the receive data outputs are squelched and held at logic ‘0’. Note: Rx Loss of Signal detection is disabled during Local Loopback and Receive Monitor Modes. Receive Loss of Lock The 78P2352 includes an optional Receiver Loss of Lock detector that will flag if the recovered Rx clock frequency differs from the reference clock by more than ±100ppm in an interval greater than 420µs. This condition is cleared when the frequencies are less than ±100ppm off for more than 500µs. Notes: 1. During Rx Loss of Signal (RLOS), the Rx Loss of Lock indicator is undefined and may report either status. 2. For reliable operation, the LOLOR bit in the Signal Control register should be toggled upon power-up and configuration. TRANSMITTER OPERATION At the media interface, the transmit driver generates an analog signal for transmission through either a transformer and 75Ω coaxial cable or directly to a fiber optics transceiver for electrical to optical conversion. At the host interface, the 78P2352 provides a number interface options for compatibility with most off-the-shelf framers and custom ASICs. A selectable 4-bit parallel or nibble interface is available with both slave or master timing options as well a serial LVPECL interface with various timing recovery modes. 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Each of the serial NRZ transmit timing modes can be configured in HW mode or SW mode as shown in the table below. Serial Mode HW Control Pins SW Control Bits SDI_PAR CKMODE PAR SMOD[1:0] Synchronous clock + data Low Low 0 00 Synchronous data only Low Floating 0 Plesiochronou s data only Low High 0 10 01 Loop-timing n/a n/a X 11 Synchronous (Re-timing) Tx Serial Modes In Figure 1, serial NRZ transmit data is input to SIDxP/N pins at LVPECL levels. By default, the data is latched in on the rising edge of SICKxP. An integrated FIFO decouples the on chip and off chip clocks and re-clocks the data using a clean synthesized clock generated from the provided reference clock. As such, the SICKxP/N clock provided by the framer/mapper IC for both channels must be source synchronous with the provided reference clock when the FIFO is used. System Reference Clock Framer/ Mapper NRZ 140 / 155 MHz NRZ 140 / 155 MHz SIxDP/N SIxCKP/N SOxCKP/N SOxDP/N CKREFP/N TDK 78P2352 CMIxP/N RXxP/N CMI CMI Coax XFMR Coax XFMR Figure 1: Synchronous clock and data available (Tx CDR bypassed, FIFO enabled) If an off-chip serial transmit clock is not available, as in Figure 2, the 78P2352 can recover a Tx clock from the serial NRZ data input and pass the data through the clock decoupling FIFO. The data is then re-clocked or re-timed using a clean synthesized clock generated from the provided reference clock. In this mode, the NRZ transmit source data for both channels must be source synchronous with the reference clock applied at CKREFP/N. System Reference Clock Framer/ Mapper CKREFP/N NRZ SIxDP/N CMIxP/N NRZ 140 / 155 MHz TDK SOxCKP/N78P2352 SOxDP/N RXxP/N CMI CMI Coax XFMR Coax XFMR Figure 2: Synchronous data only (Tx CDR enabled, FIFO enabled) Page: 5 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 5 Page 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (CONTINUED) ADDRESS 0-1: INTERRUPT CONTROL REGISTER This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as required. BIT NAME TYPE DFLT VALUE DESCRIPTION Interrupt Pin Polarity Selection: 7 INPOL R/W 0 0 : Interrupt output is active-low (default) 1 : Interrupt output is active-high 6:2 -- 1 MTLOL 0 MFERR R/W R/W R/W 01000 1 1 Reserved for future use TXLOL Error Mask (active low): Gates the TXLOL register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass FIERR Error Mask (active low): Gates the respective FIERR register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass ADDRESS 0-2: RESERVED BIT NAME TYPE DFLT VALUE 7:0 -- R/W XXXXXXX0 DESCRIPTION Reserved. Page: 11 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet 78P2352.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
78P2351	Single Channel OC-3/ STM1-E/ E4 LIU	TDK Semiconductor
78P2351R	Serial 155M NRZ to CMI Converter	Teridian Semiconductor
78P2352	Dual Channel OC-3/ STM1-E/ E4 LIU	TDK Semiconductor
78P2352	Dual Channel OC-3/ STM1-E/ E4 LIU	Teridian Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar