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Número de pieza | BSS138K | |
Descripción | N-Channel Logic Level Enhancement Mode Field Effect Transistor | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
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BSS138K
N-Channel Logic Level Enhancement Mode Field Effect
Transistor
Features
• Low On-Resistance
• Low Gate Threshold Voltage
D
• Low Input Capacitance
• Fast Switching Speed
• Low Input/Output Leakage
• Ultra-Small Surface Mount Package
• Pb Free / RoHS Compliant
G
SOT - 23
Marking : SK
S
• Green Compound
• ESD HBM = 2000 V as per JEDEC A114A; ESD CDM = 2000 V as per JEDEC C101C
Absolute Maximum Ratings(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.
Symbol
Parameter
Value
Units
VDSS
VGSS
ID
Drain-Source Voltage
Gate-Source Voltage
Drain Current
Continuous
Pulsed
50 V
±12 V
0.22
A
0.88
TJ Operating Junction Temperature Range
-55 to +150
°C
TSTG Storage Temperature Range
-55 to +150
°C
Note:
1. These ratings are limiting values above which the serviceability of any semiconductor device maybe impaired.
Thermal Characteristics
Symbol
Parameter
PD
RθJA
Note:
Total Device Dissipation
Derating above TA = 25°C
Thermal Resistance, Junction to Ambient(2)
2. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch. Minimum land pad size.
Value
350
2.8
350
Units
mW
mW/°C
°C/W
Package Marking and Ordering Information
Device Marking
SK
Device
BSS138K
Reel Size
7”
Tape Width
8 mm
Quantity
3000 units
© 2010 Fairchild Semiconductor Corporation
BSS138K Rev. 1.3.0
1
www.fairchildsemi.com
1 page Physical Dimensions
SOT-23
2.92±0.20
3
0.95
1.40
1.30+-00..1250
2.20
(0.29)
1
0.95
1.90
1.20 MAX
(0.93)
C
GAGE PLANE
0.23
0.08
0.20 MIN
(0.55)
2
0.60
0.37
0.20
A B 1.00
1.90
LAND PATTERN
RECOMMENDATION
SEE DETAIL A
0.10
0.00
0.10
C
2.40±0.30
NOTES: UNLESS OTHERWISE SPECIFIED
0.25
SEATING
PLANE
A) REFERENCE JEDEC REGISTRATION
TO-236, VARIATION AB, ISSUE H.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE INCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M - 1994.
E) DRAWING FILE NAME: MA03DREV10
SCALE: 2X
Figure 8. 3LEAD, SOT23, JEDEC TO-236, LOW PROFILE (ACTIVE)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packaging/tr/SOT23-3L_tr.pdf.
© 2010 Fairchild Semiconductor Corporation
BSS138K Rev. 1.3.0
5
www.fairchildsemi.com
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet BSS138K.PDF ] |
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