PDF AD6679 Data sheet ( Hoja de datos )

Número de pieza	AD6679
Descripción	135 MHz BW IF Diversity Receiver
Fabricantes	Analog Devices
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Data Sheet 135 MHz BW IF Diversity Receiver AD6679 FEATURES Parallel LVDS (DDR) outputs In-band SFDR = 82 dBFS at 340 MHz (500 MSPS) In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS) 1.1 W total power per channel at 500 MSPS (default settings) Noise density = −153 dBFS/Hz at 500 MSPS 1.25 V, 2.50 V, and 3.3 V dc supply operation Flexible input range 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 95 dB channel isolation/crosstalk Amplitude detect bits for efficient automatic gain control (AGC) implementation Noise shaping requantizer (NSR) option for main receiver function Variable dynamic range (VDR) option for digital predistortion (DPD) function 2 integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters Differential clock inputs Integer clock divide by 1, 2, 4, or 8 Energy saving power-down modes Small signal dither APPLICATIONS Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers GENERAL DESCRIPTION The AD6679 is a 135 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS analog-to-digital converters (ADCs) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6679 is optimized for wide input bandwidth, high sampling rates, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. AVDD1 (1.25V) AVDD2 (2.50V) FUNCTIONAL BLOCK DIAGRAM AVDD3 (3.3V) DVDD (1.25V) DRVDD (1.25V) SPIVDD (1.22V TO 3.4V) VIN+A VIN–A FD_A FD_B V_1P0 VIN+B VIN–B BUFFER ADC FAST DETECT BUFFER ADC SIGNAL MONITOR DATA ROUTER MUX SIGNAL PROCESSING DIGITAL DOWN- CONVERSION (×4) NOISE SHAPING REQUANTIZER (×2) VARIABLE DYNAMIC RANGE (×2) LVDS OUTPUT STAGING 16 LVDS OUTPUTS D0± D1± D2± D3± D4± D5± D6± D7± D8± D9± D10± D11± D12± D13± DCO± STATUS± CLK+ CLK– CLOCK GENERATION AND ADJUST ÷2 ÷4 ÷8 AGND SYNC± SPI CONTROL FAST DETECT AD6679 SIGNAL MONITOR SDIO SCLK CSB Figure 1. DGND DRGND PDWN/STBY Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD6679 AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted. Table 2. Parameter1 ANALOG INPUT FULL SCALE NOISE DENSITY2 SIGNAL-TO-NOISE RATIO (SNR)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz NSR Enabled (21% Bandwidth (BW) Mode) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz NSR Enabled (28% BW Mode) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz Temperature Min Typ Max Unit Full 2.06 V p-p Full −153 dBFS/Hz 25°C 68.9 dBFS Full 67.5 68.6 dBFS 25°C 67.8 dBFS 25°C 67.3 dBFS 25°C 63.9 dBFS 25°C 62.8 dBFS 25°C 59.0 dBFS 25°C 75.0 dBFS 25°C 74.8 dBFS 25°C 74.0 dBFS 25°C 73.1 dBFS 25°C 69.7 dBFS 25°C 68.1 dBFS 25°C 64.6 dBFS 25°C 72.4 dBFS 25°C 72.3 dBFS 25°C 71.6 dBFS 25°C 71.0 dBFS 25°C 67.7 dBFS 25°C 66.8 dBFS 25°C 63.1 dBFS 25°C 68.7 dBFS Full 67 68.5 dBFS 25°C 67.6 dBFS 25°C 67.2 dBFS 25°C 63.8 dBFS 25°C 62.5 dBFS 25°C 58.3 dBFS 25°C 11.1 Bits Full 10.8 10.9 Bits 25°C 10.8 Bits 25°C 10.8 Bits 25°C 10.3 Bits 25°C 10.1 Bits 25°C 9.5 Bits Rev. 0 \| Page 5 of 77 5 Page Data Sheet AD6679 VIN±x APERTURE DELAY N N+x N + 33 N + 34 N + 35 SYNC+ SYNC– CLK+ CLK– DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYSREF SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET tDCO tPD tCLK tCH DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP OVR+ (OVERRANGE/STAUS BIT) OVR– OVR OVR tSKEWR tSKEWF CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 2] OVR OVR OVR OVR OVR OVR A D12/D13± A D0/D1± S[N – y] S[N – x] (ODD BITS) (EVEN BITS) S[N – 1] S[N] S[N] S[N + 1] S[N + 1] S[N + 2] (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) Figure 6. Channel Multiplexed (Even/Odd) Mode—One Virtual Converter Rev. 0 \| Page 11 of 77 11 Page

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