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PDF Si3452 Data sheet ( Hoja de datos )

Número de pieza Si3452
Descripción QUAD HIGH-VOLTAGE PORT CONTROLLER
Fabricantes Silicon Laboratories 
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Si3452
QUAD HIGH-VOLTAGE PORT CONTROLLER
FOR POE AND POE+ PSES
Features
Each Si3452 high-voltage port
Programmable architecture supports
controller supports four PSE power IEEE 802.3af (PoE) and IEEE
interfaces
802.3at (PoE+) PSEs
Programmable current limits for PoE Programmable current limits for
(15.4 W), PoE+ (30 W), and
PoE (350 mA) and PoE+
proprietary systems (up to 40 W) per
(600 mA), and custom limits to
port 850 mA
I2C interface requires no external
Per-port current and voltage
MCU for easy, low-cost management
monitoring for sophisticated power
of 4 to 48 ports by the host system
management and control
Unique mixed-signal IC high-voltage Power policing mode
component integration simplifies
Robust multi-point detection
design, lowers power dissipation,
Supports 1-Event and 2-Event
minimizes external BOM, and
classification algorithms
reduces PCB footprint
Comprehensive, robust, fault-
Internal low-RON power FETs with
current-sense circuitry
Integrated transient voltage surge
suppressors
protection circuitry
Supply undervoltage lockout
(UVLO)
Output current limit and short-
Proprietary dV/dt disconnect
sensing methods
Industrial (–40 to 85 °C) operating
temperature
Compact, 6×6 mm2, 40-pin QFN
RoHS-compliant package
circuit protection
Foldback current limiting
Dual-threshold thermal overload
protection
Fault source reporting for
intelligent port management
Applications
Power over Ethernet Endpoint
Industrial automation systems
switches and Midspans for IEEE Std Networked audio
802.3af and 802.3at
IP Phone Systems and iPBXs
Supports high-power PDs, such as: Metropolitan area networked WAPs,
Pan/Tilt/Zoom security cameras
cameras, and sensors
802.11n WAPs
WiMAX ASN/BTS and CPE/ODU
Multi-band, multi-radio WAPs
systems
Security and RFID systems
Ordering Information:
See page 31.
Pin Assignments
40-Pin QFN
VEE1 1
VEE 2
VREF 3
AIN 4
AOUT 5
AGND 6
RBIAS 7
AGND 8
NC 9
VEE4 10
Si3452
(Top View)
30 VDD
29 DGND
28 AD0
27 AD1
26 AD2
25 AD2
24 AD3
23 RST
22 VEE3
21 AD3
See "9. Pin Descriptions" on page 28.
Rev. 1.5 1/15
Copyright © 2015 by Silicon Laboratories
Si3452

1 page




Si3452 pdf
Si3452
Table 2. Recommended Operating Conditions
Description
Symbol
Test Condition
Min Typ Max Unit
Ambient Operating
Temperature
TA
–40 — 85 °C
Thermal Impedance*
θJA
No airflow
1 m/s airflow
— 32 —
°C/W
— 28 —
Power Supply Voltages
VEE Supply Voltage
For IEEE 802.3af (15.4 W) apps. –57 –48 –45
V
VEE
For IEEE 802.3at (30 W) apps.
–57 –54 –51
VDD Supply Voltage
Power Supply Currents
VDD
3.0 3.3 3.6
V
VEE Supply Current
All ports on, excluding load current. — 3.7 6.0
IEE mA
All ports in shutdown mode
—1
2
VDD Supply Current
IDD
— 8 14 mA
*Note: Modeled with six parts evenly spaced on a 30 x 120 mm2, four-layer board with 25 thermal vias to a Vneg plane on the
back.
Table 3. UVLO, and Reset Specifications
Description
Symbol
Test Condition
Min Typ Max Unit
VDD Reset Threshold
VDD Power-On Ramp*
RST Input High Voltage
RST Input Low Voltage
RST Input Leakage
VRST
Ramp from 0 V to 3.0 V
RST = 0 V
— 1.75
——
0.7 x VDD
——
1
0.8
40
V
ms
V
V
μA
Reset Time Delay
TRSTDLY
Time between end of reset and
beginning of normal operation
— 100 ms
Reset Assertion Time
TRST
RST low time to generate system
reset
15
μs
VEE Monitor Accuracy
VEE UVLO Threshold
VEEMON
VUVLO
Measured VEE relative to actual
VEE for VEE (–44 to –57 V)
Point at which VEE UVLO is
declared.
VEE going negative
VEE going positive
–4 —
–38 –36
— –33
4
–31
%
V
*Note: If VDD ramp time is slower than 1 ms, hold the reset pins low until VDD is above 3.0 V to insure proper reset
operation.
Rev. 1.5
5

5 Page





Si3452 arduino
2. PSE System-Level Diagrams
Si3452
Host
Controller
I2C
SDA
SCL
INT
Si8405 Digital
Isolator
RST
PSE State
Machines
I2C and
Measurement
Subsystem
OTP
RAM
Mixed Signal
Resources
Si3452
Figure 2. 4-Port System with Direct Host Connection
3. PSE Application Diagrams
Host / Switch
Si8405
Bidirectional
Isolator
1.1 V
(e.g. TLV431)
+3.3 V
4x10 k
Tie high
or low to
select
address
AD0
AD1
AD2
AD3
SCL
SDA
INT
RST
VREF
VDD AGND DGND
GND12/34
Si3452
DET4
DET3
DET2
DET1
RBIAS
44.2 k
1% VEE VEE[4:1] VOUT4 VOUT3 VOUT2 VOUT1
–54 V
PORT1
PORT2
PORT3
PORT4
Figure 3. 4-Port Application Diagram Using dV/dt Disconnect and I2C Host Interface
Rev. 1.5
11

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