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STMP3610XXLAEB1N 데이터시트 PDF




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기능 Audio System on Chip
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STMP3610XXLAEB1N 데이터시트, 핀배열, 회로
PRODUCT DATA SHEET
STMP36xx
Audio System on Chip
with USB OTG, LCD, Hard Drive, and Battery Charger
Fourth-Generation Audio Decoder
Version 1.02 May 3, 2006
FM Tuner
Host Processor (Optional)
Rechargeable
Battery
LED/LCD/Color
Display
Hi-Speed USB
On-the-Go
Microphone
Voice Record
NAND Flash
SDRAM/NOR
SPDIF
Hard Drive
SD/SDIO/MS
Buttons/Switches
Headphones
ISO9001:2000 Certified
IEC QC 080000:2005
(IECQ HSPM) Certified
OFFICIAL PRODUCT DOCUMENTATION 5/3/06
5-36xx-D1-1.02-050306
Copyright © 2003-2006 SigmaTel, Inc.
All rights reserved.
SigmaTel, Inc. makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes
no commitment to update the information contained herein. SigmaTel reserves the right to change or discontinue this product at any time, without no-
tice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document.
The following are trademarks of SigmaTel, Inc., and may be used to identify SigmaTel products only: SigmaTel, the SigmaTel Logo, C Major, D Major
and Go-Chip. Windows Media and the Windows logo are trademarks or registered trademarks of Microsoft Corporation in the United States and/or
other countries. Other product and company names contained herein may be trademarks of their respective owners.
Free Datasheet http://www.datasheet4u.com/




STMP3610XXLAEB1N pdf, 반도체, 판매, 대치품
OFFICIAL PRODUCT DOCUMENTATION 5/3/06
STMP36xx
4.7. Integrated USB 2.0 PHY Initialization Flow Charts ......................................................................... 54
4.8. Clocking During Reset .................................................................................................................... 55
4.9. Programmable Registers ................................................................................................................ 56
4.9.1. PLL Control Register 0 Description ................................................................................... 56
4.9.2. PLL Control Register 1 Description ................................................................................... 58
4.9.3. CPU Clock Control Register Description ........................................................................... 58
4.9.4. AHB, APBH Bus Clock Control Register Description ........................................................ 59
4.9.5. APBX Clock Control Register Description ......................................................................... 61
4.9.6. XTAL Clock Control Register Description ......................................................................... 62
4.9.7. On-Chip SRAM Clock Control Register Description .......................................................... 63
4.9.8. UTMI Clock Control Register Description .......................................................................... 63
4.9.9. Synchronous Serial Port Clock Control Register Description ............................................ 64
4.9.10. General-Purpose Media Interface Clock Control Register Description ........................... 65
4.9.11. SPDIF Clock Control Register Description ...................................................................... 66
4.9.12. EMI Clock Control Register Description .......................................................................... 67
4.9.13. IR Clock Control Register Description ............................................................................. 67
5. INTERRUPT COLLECTOR ........................................................................................................... 69
5.1. Overview ......................................................................................................................................... 69
5.2. Nesting of Multi-Level IRQ Interrupts .............................................................................................. 72
5.3. FIQ Generation ............................................................................................................................... 73
5.4. Interrupt Sources ............................................................................................................................ 75
5.5. CPU Wait-for-Interrupt Mode .......................................................................................................... 77
5.6. Behavior During Reset .................................................................................................................... 77
5.7. Programmable Registers ................................................................................................................ 78
5.7.1. Interrupt Collector Interrupt Vector Address Register Description .................................... 78
5.7.2. Interrupt Collector Level Acknowledge Register Description ............................................ 78
5.7.3. Interrupt Collector Control Register Description ................................................................ 79
5.7.4. Interrupt Collector Status Register Description ................................................................. 81
5.7.5. Interrupt Collector Raw Interrupt Input Register 0 Description .......................................... 82
5.7.6. Interrupt Collector Raw Interrupt Input Register 1 Description .......................................... 83
5.7.7. Interrupt Collector Priority Register 0 Description ............................................................. 83
5.7.8. Interrupt Collector Priority Register 1 Description ............................................................. 85
5.7.9. Interrupt Collector Priority Register 2 Description ............................................................. 86
5.7.10. Interrupt Collector Priority Register 3 Description ........................................................... 88
5.7.11. Interrupt Collector Priority Register 4 Description ........................................................... 90
5.7.12. Interrupt Collector Priority Register 5 Description ........................................................... 91
5.7.13. Interrupt Collector Priority Register 6 Description ........................................................... 93
5.7.14. Interrupt Collector Priority Register 7 Description ........................................................... 95
5.7.15. Interrupt Collector Priority Register 8 Description ........................................................... 96
5.7.16. Interrupt Collector Priority Register 9 Description ........................................................... 98
5.7.17. Interrupt Collector Priority Register 10 Description ....................................................... 100
5.7.18. Interrupt Collector Priority Register 11 Description ....................................................... 101
5.7.19. Interrupt Collector Priority Register 12 Description ....................................................... 103
5.7.20. Interrupt Collector Priority Register 13 Description ....................................................... 105
5.7.21. Interrupt Collector Priority Register 14 Description ....................................................... 106
5.7.22. Interrupt Collector Priority Register 15 Description ....................................................... 108
5.7.23. Interrupt Collector Interrupt Vector Base Address Register Description ....................... 110
5.7.24. Interrupt Collector Debug Register 0 Description .......................................................... 110
5.7.25. Interrupt Collector Debug Read Register 0 Description ................................................ 112
5.7.26. Interrupt Collector Debug Read Register 1 Description ................................................ 112
5.7.27. Interrupt Collector Debug Flag Register Description ..................................................... 113
5.7.28. Interrupt Collector Debug Read Request Register 0 Description .................................. 113
5.7.29. Interrupt Collector Debug Read Request Register 1 Description .................................. 114
6. DEFAULT FIRST-LEVEL PAGE TABLE FOR ARM926 MMU .................................................. 115
6.1. Overview ....................................................................................................................................... 115
6.2. 16-Megabyte Page-Mapped Virtual Memory (0xFFXXXXXX) ...................................................... 117
6.2.1. Default First-Level Page Table Entry 4095 ..................................................................... 118
6.2.2. Default First-Level Page Table Entries 4094–4080 ........................................................ 119
6.2.3. Default First-Level Page Table PIO Register Map Entry 2048 ........................................ 120
6.2.4. Default First-Level Page Table Entry 0000 V==R SRAM Access ................................... 121
4
Contents
5-36xx-D1-1.02-050306
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STMP3610XXLAEB1N 전자부품, 판매, 대치품
OFFICIAL PRODUCT DOCUMENTATION 5/3/06
STMP36xx
10.5.30. AHB-to-APBH DMA Channel 3 Debug Register 1 Description ................................... 225
10.5.31. AHB-to-APBH DMA Channel 3 Debug Register 2 Description ................................... 226
10.5.32. APBH DMA Channel 4 Current Command Address Register Description .................. 227
10.5.33. APBH DMA Channel 4 Next Command Address Register Description ....................... 228
10.5.34. APBH DMA Channel 4 Command Register Description ............................................. 228
10.5.35. APBH DMA Channel 4 Buffer Address Register Description ...................................... 230
10.5.36. APBH DMA Channel 4 Semaphore Register Description ........................................... 231
10.5.37. AHB-to-APBH DMA Channel 4 Debug Register 1 Description ................................... 232
10.5.38. AHB-to-APBH DMA Channel 4 Debug Register 2 Description ................................... 233
10.5.39. APBH DMA Channel 5 Current Command Address Register Description .................. 234
10.5.40. APBH DMA Channel 5 Next Command Address Register Description ....................... 235
10.5.41. APBH DMA Channel 5 Command Register Description ............................................. 235
10.5.42. APBH DMA Channel 5 Buffer Address Register Description ...................................... 237
10.5.43. APBH DMA Channel 5 Semaphore Register Description ........................................... 238
10.5.44. AHB-to-APBH DMA Channel 5 Debug Register 1 Description ................................... 239
10.5.45. AHB-to-APBH DMA Channel 5 Debug Register 2 Description ................................... 240
10.5.46. APBH DMA Channel 6 Current Command Address Register Description .................. 241
10.5.47. APBH DMA Channel 6 Next Command Address Register Description ....................... 242
10.5.48. APBH DMA Channel 6 Command Register Description ............................................. 242
10.5.49. APBH DMA Channel 6 Buffer Address Register Description ...................................... 244
10.5.50. APBH DMA Channel 6 Semaphore Register Description ........................................... 245
10.5.51. AHB-to-APBH DMA Channel 6 Debug Register 1 Description ................................... 246
10.5.52. AHB-to-APBH DMA Channel 6 Debug Register 2 Description ................................... 247
10.5.53. APBH DMA Channel 7 Current Command Address Register Description .................. 248
10.5.54. APBH DMA Channel 7 Next Command Address Register Description ....................... 249
10.5.55. APBH DMA Channel 7 Command Register Description ............................................. 249
10.5.56. APBH DMA Channel 7 Buffer Address Register Description ...................................... 251
10.5.57. APBH DMA Channel 7 Semaphore Register Description ........................................... 252
10.5.58. AHB-to-APBH DMA Channel 7 Debug Register 1 Description ................................... 253
10.5.59. AHB-to-APBH DMA Channel 7 Debug Register 2 Description ................................... 254
11. AHB-TO-APBX BRIDGE WITH DMA ......................................................................................... 257
11.1. Overview ..................................................................................................................................... 257
11.2. APBX DMA ................................................................................................................................. 258
11.3. DMA Chain Example ................................................................................................................... 261
11.4. Behavior During Reset ................................................................................................................ 262
11.5. Programmable Registers ............................................................................................................ 263
11.5.1. AHB-to-APBX Bridge Control and Status Register 0 Description ................................. 263
11.5.2. AHB-to-APBX Bridge Control and Status Register 1 Description ................................. 264
11.5.3. AHB-to-APBX DMA Device Assignment Register Description ...................................... 266
11.5.4. APBX DMA Channel 0 Current Command Address Register Description .................... 267
11.5.5. APBX DMA Channel 0 Next Command Address Register Description ......................... 267
11.5.6. APBX DMA Channel 0 Command Register Description ............................................... 268
11.5.7. APBX DMA Channel 0 Buffer Address Register Description ........................................ 270
11.5.8. APBX DMA Channel 0 Semaphore Register Description ............................................. 270
11.5.9. AHB-to-APBX DMA Channel 0 Debug Register 1 Description ...................................... 271
11.5.10. AHB-to-APBX DMA Channel 0 Debug Register 2 Description .................................... 273
11.5.11. APBX DMA Channel 1 Current Command Address Register Description .................. 274
11.5.12. APBX DMA Channel 1 Next Command Address Register Description ....................... 275
11.5.13. APBX DMA Channel 1 Command Register Description ............................................. 275
11.5.14. APBX DMA Channel 1 Buffer Address Register Description ...................................... 277
11.5.15. APBX DMA Channel 1 Semaphore Register Description ........................................... 277
11.5.16. AHB-to-APBX DMA Channel 1 Debug Register 1 Description .................................... 278
11.5.17. AHB-to-APBX DMA Channel 1 Debug Register 2 Description .................................... 280
11.5.18. APBX DMA Channel 2 Current Command Address Register Description .................. 281
11.5.19. APBX DMA Channel 2 Next Command Address Register Description ....................... 282
11.5.20. APBX DMA Channel 2 Command Register Description ............................................. 282
11.5.21. APBX DMA Channel 2 Buffer Address Register Description ...................................... 284
11.5.22. APBX DMA Channel 2 Semaphore Register Description ........................................... 284
11.5.23. AHB-to-APBX DMA Channel 2 Debug Register 1 Description .................................... 285
11.5.24. AHB-to-APBX DMA Channel 2 Debug Register 2 Description .................................... 287
11.5.25. APBX DMA Channel 3 Current Command Address Register Description .................. 288
11.5.26. APBX DMA Channel 3 Next Command Address Register Description ....................... 289
5-36xx-D1-1.02-050306
Contents
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관련 데이터시트

부품번호상세설명 및 기능제조사
STMP3610XXLAEB1M

Audio System on Chip

Sigmatel
Sigmatel
STMP3610XXLAEB1N

Audio System on Chip

Sigmatel
Sigmatel

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