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부품번호 | H5TQ5163MFR-16C 기능 |
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기능 | 512Mb DDR3 SDRAM | ||
제조업체 | Hynix Semiconductor | ||
로고 | |||
H5TQ(S)5163MFR
512Mb DDR3 SDRAM
H5TQ(S)5163MFR
** Since DDR3 Specification has not been defined completely yet
in JEDEC, this document may contain items under discussion.
** Contents may be changed at any time without any notice.
Rev. 1.0 / Oct 2008
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
1
H5TQ(S)5163MFR
6. AC and DC Output Measurement Levels
6.1 Single Ended AC and DC Output Levels
6.1.1 Differential AC and DC Output Levels
6.2 Single Ended Output Slew Rate
6.3 Differential Output Slew Rate
6.4 Reference Load for AC Timing and Output Slew Rate
7. Overshoot and Undershoot Specifications
7.1 Address and Control Overshoot and Undershoot Specifications
7.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
7.3 34 ohm Output Driver DC Electrical Characteristics
7.4 Output Driver Temperature and Voltage sensitivity
7.5 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.1 On-Die Termination (ODT) Levels and I-V Characteristics
7.5.2 ODT DC Electrical Characteristics
7.5.3 ODT Temperature and Voltage sensitivity
7.6 ODT Timing Definitions
7.6.1 Test Load for ODT Timings
7.6.2 ODT Timing Reference Load
8. IDD Specification Parameters and Test Conditions
8.1 IDD Measurement Conditions
8.2 IDD Specifications
8.2.1 IDD6 Current Definition
8.2.2 IDD6TC Specification (see notes 1~2)
9. Input/Output Capacitance
10. Standard Speed Bins
11. Electrical Characteristics and AC Timing
12. Package Dimensions
Rev. 1.0 / Oct 2008
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4페이지 H5TQ(S)5163MFR
1.3 ROW AND COLUMN ADDRESS TABLE
512Mb
Configuration
# of Banks
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page size 1
32Mb x 16
8
BA0 - BA2
A10/AP
A12/BC#
A0 - A11
A0 - A9
2 KB
Note1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG ÷ 8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Rev. 1.0 / Oct 2008
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부품번호 | 상세설명 및 기능 | 제조사 |
H5TQ5163MFR-16C | 512Mb DDR3 SDRAM | Hynix Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |