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ST7LITE39 데이터시트 PDF : 부품 기능 및 핀배열

부품번호 ST7LITE39
기능 8-BIT MCU
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ST7LITE39 데이터시트 및 ST7LITE39 PDF

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ST7LITE39 pdf, 반도체, 판매, 대치품
ST7LITE3
1 INTRODUCTION
The ST7LITE3 is a member of the ST7 microcon-
troller family. All ST7 devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.
The ST7LITE3 features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.
Under software control, the ST7LITE3 device can
be placed in WAIT, SLOW, or HALT mode, reduc-
ing power consumption when the application is in
idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
Figure 1. General Block Diagram
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 129.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
CLKIN
OSC1
OSC2
VDD
VSS
RESET
Int.
1% RC
1MHz
PLL x 8
or PLL X4
Ext.
OSC
1MHz
to
16MHz
/2
LVD
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
Internal
CLOCK
PROGRAM
MEMORY
(8K Bytes)
RAM
(384 Bytes)
12-Bit
Auto-Reload
TIMER 2
8-Bit
LITE TIMER 2
PORT A
PORT B
ADC
Debug Module
SPI
LINSCI
WDG
DATA EEPROM
( 256 Bytes)
PA7:0
(8 bits)
PB6:0
(7 bits)
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1

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ST7LITE39 전자부품, 판매, 대치품
ST7LITE3
Pin
No.
Pin Name
Level
Port / Control
Main
Input
Output Function
(after
reset)
Alternate Function
PA6 /MCO/
12 ICCCLK/
BREAK
I/O CT
X
ei1
13
PA5 /ATPWM3/
ICCDATA
I/O
CT
HS
14 PA4/ATPWM2 I/O CT HS
15 PA3/ATPWM1 I/O CT HS
16 PA2/ATPWM0 I/O CT HS
17 PA1/ATIC
I/O CT HS
18 PA0/LTIC
I/O CT HS
19 OSC2
O
X
X
X
X
X
X
ei0
X
20 OSC1/CLKIN I
Main Clock Output or In Circuit Commu-
nication Clock or External BREAK
Caution: During normal operation this
pin must be pulled- up, internally or ex-
X X Port A6 ternally (external pull-up of 10k manda-
tory in noisy environment). This is to
avoid entering ICC mode unexpectedly
during a reset. In the application, even if
the pin is configured as output, any re-
set will put it back in input pull-up.
X
X Port A5
Auto-Reload Timer PWM3 or In Circuit
Communication Data
X X Port A4 Auto-Reload Timer PWM2
X X Port A3 Auto-Reload Timer PWM1
X X Port A2 Auto-Reload Timer PWM0
X X Port A1 Auto-Reload Timer Input Capture
X X Port A0 Lite Timer Input Capture
Resonator oscillator inverter output
Resonator oscillator inverter input or External clock
input
Note:
For input with interrupt possibility “eix” defines the associated external interrupt vector which can be as-
signed to one of the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating
defined through option register OR.
7/167
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