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PDF ST7LITE30F2 Data sheet ( Hoja de datos )

Número de pieza ST7LITE30F2
Descripción 8-BIT MCU
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! ST7LITE30F2 Hoja de datos, Descripción, Manual

ST7LITE3xF2
8-bit MCU with single voltage Flash, data EEPROM, ADC, timers,
SPI, LINSCI
Features
Memories
– 8 Kbytes program memory: single voltage ex-
tended Flash (XFlash) Program memory with
read-out protection, In-Circuit Programming
and In-Application programming (ICP and
IAP), data retention: 20 years at 55°C.
– 384 bytes RAM
– 256 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: Internal RC 1% oscillator,
crystal/ceramic resonator or external clock
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– Five Power Saving Modes: Halt, Active-Halt,
Wait and Slow, Auto Wake Up From Halt
I/O Ports
– Up to 15 multifunctional bidirectional I/O lines
– 7 high sink outputs
5 Timers
– Configurable Watchdog Timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWM
outputs, input capture and output compare
functions
QFN20
SO20
DIP20
2 Communication Interfaces
– Master/slave LINSCIasynchronous serial
interface
– SPI synchronous serial interface
Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 12 external interrupt lines (on 4 vectors)
A/D Converter
– 7 input channels
– 10-bit resolution
Instruction Set
8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
Development Tools
– Full hardware/software development package
– DM (Debug module)
Table 1. Device summary
Features
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
ST7LITE30F2
ST7LITE35F2
ST7LITE39F2
8K
384 (128)
- - 256
Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit ADC
2.7V to 5.5V
Up to 8Mhz
(w/ ext OSC up to 16MHz)
Up to 8Mhz (w/ ext OSC up to 16MHz
and int 1MHz RC 1% PLLx8/4MHz)
-40°C to +125°C
SO20 300”, DIP20, QFN20
Rev. 9
November 2007
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1 page




ST7LITE30F2 pdf
ST7LITE3xF2
1 INTRODUCTION
The ST7LITE3 is a member of the ST7 microcon-
troller family. All ST7 devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.
The ST7LITE3 features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.
Under software control, the ST7LITE3 device can
be placed in WAIT, SLOW, or HALT mode, reduc-
ing power consumption when the application is in
idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
Figure 1. General Block Diagram
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 131.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
CLKIN
OSC1
OSC2
VDD
VSS
RESET
Int.
1% RC
1MHz
PLL x 8
or PLL X4
Ext.
OSC
1MHz
to
16MHz
/2
LVD
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
Internal
CLOCK
PROGRAM
MEMORY
(8K Bytes)
RAM
(384 Bytes)
12-Bit
Auto-Reload
TIMER 2
8-Bit
LITE TIMER 2
PORT A
PORT B
ADC
Debug Module
SPI
LINSCI
WDG
DATA EEPROM
( 256 Bytes)
PA7:0
(8 bits)
PB6:0
(7 bits)
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ST7LITE30F2 arduino
ST7LITE3xF2
Address Block
Register
Label
Register Name
0031h
0032h
0033h
SPIDR
SPI SPICR
SPICSR
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
0037h
ITC EICR
0038h
MCC MCCSR
0039h Clock and RCCR
003Ah Reset SICSR
003Bh
003Ch
ITC EISR
003Dh to
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
LINSCI
(LIN Mas-
ter/Slave)
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR
0048h
0049h
004Ah
AWU
AWUPR
AWUCSR
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DM3)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
0051h to
007Fh
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
A/D Control Status Register
A/D Data Register High
A/D control and Data Register Low
External Interrupt Control Register
Main Clock Control/Status Register
RC oscillator Control Register
System Integrity Control/Status Register
Reserved area (1 byte)
External Interrupt Selection Register
Reserved area (3 bytes)
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
Reserved area (1 byte)
AWU Prescaler Register
AWU Control/Status Register
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
Reserved area (47 bytes)
Reset Status Remarks
xxh
0xh
00h
00h
xxh
x0h
00h
00h
FFh
0110 0xx0b
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
00h R/W
C0h
xxh
00xx xxxxb
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFh R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the DM registers, see the ST7 ICC Reference Manual.
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