PDF RTM870T-691 Data sheet ( Hoja de datos )

Número de pieza	RTM870T-691
Descripción	TSSOP56 low power main clock
Fabricantes	RealTek
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1. RTM870T-691 pinout datasheet Hay una vista previa y un enlace de descarga de RTM870T-691 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas
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General Description RTM870T-691 is a TSSOP56 low power main clock for ATI RS600 system using AMD K8 processors & SB600 Southbridge Output Features: z 3 – REF clock z 2 – USB 48MHz clock z 1 – Hyper Transport 66MHz clock seed z 6 – 0.8V push-pull differential SRCCLK pairs z 2 – 0.8V push-pull differential ATIGCLK pairs z 2– 3.3V push-pull differential CPUCLK pairs AC Specifications: z CPUCLK outputs Cycle-to-Cycle jitter < 100ps z SRCCLK outputs Cycle-to-Cycle jitter < 125ps z ATIGCLK outputs Cycle-to-Cycle jitter < 125ps z REF outputs Cycle-to-Cycle jitter < 200ps z HTT outputs Cycle-to-Cycle jitter < 180ps z 48MHz USB outputs Cycle-to-Cycle jitter < 130ps z +/- 300ppm Frequency accuracy on CPU, SRC, ATIG clocks RTM870T-691 GNDREF 1 VDDREF 2 X1 3 X2 4 VDD48 5 Mode/48MHz_0 6 Sync/48MHz_1 7 GND48 8 SCLK 9 SDAT 10 RESET# 11 SRCCLK_7 12 SRCCLK_7# 13 VDDSRC 14 GNDSRC 15 SRCCLK_6 16 SRCCLK_6# 17 SRCCLK_5 18 SRCCLK_5# 19 SRCCLK_4 20 SRCCLK_4# 21 GNDSRC 22 VDDSRC 23 SRCCLK_2 24 SRCCLK_2# 25 VDDSRC 26 GNDSRC 27 CLKREQB# 28 56 FSA/REF_0 55 FSB/REF_1 54 FSC/REF_2 53 NC 52 VDDHTT 51 HTTCLK_0 50 GNDHTT 49 CLKREQA# 48 CPUCLK8_0 47 CPUCLK8_0# 46 VDDCPU 45 GNDCPU 44 CPUCLK8_1 43 CPUCLK8_1# 42 VDDA 41 GNDA 40 IREF (*Turbo) 39 SRCCLK_0 38 SRCCLK_0# 37 GNDSRC 36 VDDSRC 35 ATIGCLK_0 34 ATIGCLK_0# 33 VDDATIG 32 GNDATIG 31 ATIGCLK_1 30 ATIGCLK_1# 29 CLKREQC# Option Function Mode(PIN6) PIN40 0 NC 1 Turbo Application Features: z 3 – Clock Request pins for SRC and ATIG clocks z Spread Spectrum for EMI reduction z Outputs controllable by SMBus SRC Output Control Control REQ# Register REQ# 0(default) 1 0 by register enable 1(default) by register disable Frequency Table FSC 0 FSB 0 FSA CPU 0 266.67 0 0 1 133.33 0 1 0 200.00 0 1 1 166.67 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 1 1 1 200.00 HTT 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 SRC 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 ATIG 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 USBI 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 SSC +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% +/- 0.25% 2006/10/12 Confidential 1 v.1.4 1 page RTM870T-691 Address CR 03h [3] Output Control (00) Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description CLKREQ_A# Controls SRCCLK_7 0 = Does not control 1 = Controls CLKREQ_A# Controls SRCCLK_6 0 = Does not control 1 = Controls CLKREQ_A# Controls SRCCLK_5 0 = Does not control 1 = Controls CLKREQ_A# Controls SRCCLK_4 0 = Does not control 1 = Controls Reserved CLKREQ_B# Controls SRCCLK_2 0 = Does not control 1 = Controls Reserved CLKREQ_B# Controls SRCCLK_0 0 = Does not control 1 = Controls Pin 12,13 16,17 18,19 20,21 - 24,25 - 38,39 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Address CR 04h [4] Output Control (00) Bit Bit7 Bit6 Bit5 Bit4 Bit[3:0] Description Reserved CLKREQ_C# Controls ATIGCLK_1 0 = Does not control 1 = Controls CLKREQ_C# Controls ATIGCLK_0 0 = Does not control 1 = Controls Reserved Reserved Pin - 30,31 34,35 - - Type R/W R/W R/W R/W R/W Default 0 0 0 0 0000 Address CR 05h [5] Output Control (00) Bit Bit[7:4] Bit3 Bit2 Bit1 Bit0 Description Resvered Differential Ouptut Disable Mode of CPUCLK1 0 = Driven 1 = Hi-Z Differential Ouptut Disable Mode of CPUCLK0 0 = Driven 1 = Hi-Z Reserved Differential Ouptut Disable Mode of SRCCLK[7:0] and ATIGCLK[3:0] 0 = Driven 1 = Hi-z Pin - - - - - Type R/W R/W R/W R/W R/W Default 0000 0 0 0 0 2006/10/12 Confidential 5 v.1.4 5 Page RTM870T-691 Address CR 15h [21] Group delay control (00) Bit Bit[7:4] Bit[3:0] Description CPU-0 group delay selection by 75 ps base CPU-1 group delay selection by 75 ps base Skew delay = base x ( delay-selection ) Type R/W R/W Default 0000 0000 Address CR 16h [22] Group delay control (00) Bit Bit[7:4] Bit[3:0] Reserved Description SRC[7:0] group delay selection by 75 ps base Skew delay = base x ( delay-selection ) Type R/W R/W Default 0000 0000 Address CR 17h [23] Group delay control (00) Bit Bit[7:6] Bit[5:4] Bit[3:0] 00 = HTT duty positive duty = 50% 01 = HTT duty positive duty = 48.3% 10 = HTT duty positive duty = 47.8% 11 = HTT duty positive duty = 46.7% Reserved Description ATIG[3:0] delay selection by 75 ps base Skew delay = base x ( delay-selection ) TYPE R/W R/W R/W Default 00 00 0000 Address CR 18h [24] PLL2 M code (00) Bit Bit[7:0] reserved Description Type Default R/W 0000-0000 Address CR 19h [25] PLL2 M/N code (00) Bit Bit[7:0] reserved Description Type Default R/W 0000-0000 Address CR 1ah [26] (A0) Bit Bit[7:6] Bit[5:4] Bit[3:2] Bit[1:0] Description 00 = 48MHz[1:0] PAD driving 1.00X 01 = 48MHz[1:0] PAD driving 1.25X 10 = 48MHz[1:0] PAD driving 1.50X 11 = 48MHz[1:0] PAD driving 2.00X 00 = HTT PAD driving 1.00X 01 = HTT PAD driving 1.25X 10 = HTT PAD driving 1.50X 11 = HTT PAD driving 2.00X 00 = REF[2:0] PAD driving 1.00X 01 = REF[2:0] PAD driving 1.25X 10 = REF[2:0] PAD driving 1.50X 11 = REF[2:0] PAD driving 2.00X Reserved Type R/W R/W R/W R/W Default 10 10 00 00 2006/10/12 Confidential 11 v.1.4 11 Page

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