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부품번호 | KSZ8995X 기능 |
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기능 | Integrated 5-Port 10/100 QoS Switch | ||
제조업체 | Micrel Semiconductor | ||
로고 | |||
전체 30 페이지수
KS8995X
Micrel
KS8995X
Integrated 5-Port 10/100 QoS Switch
Rev. 1.13
General Description
The KS8995X is a highly integrated Layer-2 QoS (Quality of
Service) switch with optimized BOM (Bill of Materials) cost for
low port count, cost-sensitive 10/100Mbps switch systems. It
also provides an extensive feature set including three differ-
ent QoS priority schemes, a dual MII interface for BOM cost
reduction, rate limiting to offload CPU tasks, software and
hardware power-down, a MDC/MDIO control interface and
port mirroring/monitoring to effectively address both current
and emerging Fast Ethernet applications.
The KS8995X contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five MAC (Media
Access Control) units, a high-speed non-blocking switch
fabric, a dedicated address lookup engine, and an on-chip
frame buffer memory.
All PHY units support 10BaseT and 100BaseTX. In addition,
two of the PHY units support 100BaseFX (Ports 4 and 5).
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Features
• Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully non-
blocking configuration
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in
Ports 4 and 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode
MII) and MII-P5 (PHY mode MII)
• VLAN ID tag/untag options, per-port basis
• Enable/disable option for huge frame size up to 1916
bytes per frame
• Broadcast storm protection with percent control – global
and per-port basis
• Optimization for fiber-to-copper media conversion
• Full-chip hardware power-down support (register
configuration not saved)
• Per-port-based software power-save on PHY (idle link
detection, register configuration preserved)
• QoS/CoS packets prioritization supports: per port,
802.1p and DiffServ based
Functional Diagram
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
MII-P5
MDC, MDI/O
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
LED I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
Control
Registers
1K look-up
Engine
Queue
Mgmnt
Buffer
Mgmnt
Frame
Buffers
EEPROM
I/F
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
December 2003
1
M9999-120403
KS8995X
Micrel
Table of Contents
System Level Applications .............................................................................................................................................................. 6
Pin Description (by Number) ........................................................................................................................................................... 8
Pin Description (by Name) ............................................................................................................................................................ 13
Pin Configuration ........................................................................................................................................................................... 18
Introduction ............................................................................................................................................................................ 19
Functional Overview: Physical Layer Transceiver ..................................................................................................................... 19
100BaseTX Transmit ............................................................................................................................................................... 19
100BaseTX Receive ................................................................................................................................................................ 19
PLL Clock Synthesizer ............................................................................................................................................................ 19
Scrambler/De-scrambler (100BaseTX only) ............................................................................................................................ 19
100BaseFX Operation ............................................................................................................................................................. 19
100BaseFX Signal Detection ................................................................................................................................................... 20
100BaseFX Far End Fault ....................................................................................................................................................... 20
10BaseT Transmit ................................................................................................................................................................... 20
10BaseT Receive .................................................................................................................................................................... 20
Power Management ................................................................................................................................................................ 20
MDI/MDI-X Auto Crossover ..................................................................................................................................................... 20
Auto-Negotiation ...................................................................................................................................................................... 20
Functional Overview: Switch Core ............................................................................................................................................... 21
Address Look Up ..................................................................................................................................................................... 21
Learning ............................................................................................................................................................................ 21
Migration ............................................................................................................................................................................ 21
Aging
............................................................................................................................................................................ 21
Switching Engine ..................................................................................................................................................................... 21
MAC (Media Access Controller) Operation ............................................................................................................................. 22
Inter-Packet Gap ............................................................................................................................................................. 22
Backoff Algorithm ............................................................................................................................................................ 22
Late Collision .................................................................................................................................................................. 22
Illegal Frame ................................................................................................................................................................... 22
Flow Control .................................................................................................................................................................... 22
Half-Duplex Back Pressure ............................................................................................................................................. 22
Broadcast Storm Protection ............................................................................................................................................ 23
MII Interface Operation .................................................................................................................................................................. 23
SNI Interface Operation ................................................................................................................................................................. 25
Advanced Functionality ................................................................................................................................................................. 25
QoS Support ............................................................................................................................................................................ 25
Rate Limit Support ................................................................................................................................................................... 27
Configuration Interface ............................................................................................................................................................ 28
I2C Master Serial Bus Configuration ............................................................................................................................... 28
MII Management Interface (MIIM) .................................................................................................................................................. 28
Register Map ............................................................................................................................................................................ 29
Global Registers ...................................................................................................................................................................... 29
Register 0 (0x00): Chip ID0 ............................................................................................................................................ 29
Register 1 (0x01): Chip ID1/Start Switch ....................................................................................................................... 29
Register 2 (0x02): Global Control 0 ................................................................................................................................ 29
Register 3 (0x03): Global Control 1 ................................................................................................................................ 30
Register 4 (0x04): Global Control 2 ................................................................................................................................ 31
Register 5 (0x05): Global Control 3 ................................................................................................................................ 31
Register 6 (0x06): Global Control 4 ................................................................................................................................ 32
Register 7 (0x07): Global Control 5 ................................................................................................................................ 32
M9999-120403
4 December 2003
4페이지 KS8995X
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
10/100
PHY 1
10/100
PHY 2
10/100
PHY 3
10/100
PHY 4
10/100
PHY 5
EEPROM
I/F
5-port
LAN
EEPROM
KS8995X
Figure 3. Standalone Switch
Micrel
December 2003
7
M9999-120403
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ KSZ8995X.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
KSZ8995M | Integrated 5-Port 10/100 Managed Switch | Micrel Semiconductor |
KSZ8995X | Integrated 5-Port 10/100 QoS Switch | Micrel Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |