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PDF ATtiny828 Data sheet ( Hoja de datos )
| Número de pieza | ATtiny828 | |
| Descripción | 8-bit AVR Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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ATtiny828
8-bit AVR Microcontroller with 8K Bytes In-System
Programmable Flash
Features
DATASHEET
z High Performance, Low Power Atmel® AVR® 8-bit Microcontroller
z Advanced RISC Architecture
z 123 Powerful Instructions – Most Single Clock Cycle Execution
z 32 x 8 General Purpose Working Registers
z Fully Static Operation
z Up to 20 MIPS Throughput at 20 MHz
z Non-volatile Program and Data Memories
z 8K Bytes of In-System Programmable Flash Program Memory
z Endurance: 10,000 Write/Erase Cycles
z 256 Bytes of In-System Programmable EEPROM
z Endurance: 100,000 Write/Erase Cycles
z 512 Bytes Internal SRAM
z Optional Boot Code Section with Independent Lock Bits
z Data Retention: 20 Years at 85oC / 100 Years at 25oC
z Peripheral Features
z One 8-bit and one 16-bit Timer/Counter with Two PWM Channels, Each
z Programmable Ultra Low Power Watchdog Timer
z On-chip Analog Comparator
z 10-bit Analog to Digital Converter
z 28 External and 4 Internal, Single-ended Input Channels
z Full Duplex USART with Start Frame Detection
z Master/Slave SPI Serial Interface
z Slave I2C Serial Interface
z Special Microcontroller Features
z Low Power Idle, ADC Noise Reduction, and Power-down Modes
z Enhanced Power-on Reset Circuit
z Programmable Brown-out Detection Circuit with Supply Voltage Sampling
z External and Internal Interrupt Sources
z Pin Change Interrupt on 28 Pins
z Calibrated 8MHz Oscillator with Temperature Calibration Option
z Calibrated 32kHz Ultra Low Power Oscillator
z High-Current Drive Capability on 8 I/O Pins
z I/O and Packages
z 32-lead TQFP, and 32-pad QFN/MLF: 28 Programmable I/O Lines
z Speed Grade
z 0 – 2 MHz @ 1.7 – 1.8V
z 0 – 4 MHz @ 1.8 – 5.5V
z 0 – 10 MHz @ 2.7 – 5.5V
z 0 – 20 MHz @ 4.5 – 5.5V
8371A–AVR–08/12
1 page  
2. Overview
ATtiny828 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny828 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Figure 3.
VCC
Block Diagram
RESET GND
POWER
SUPERVISION:
POR
BOD
RESET
CALIBRATED ULP
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
MEMORY
(FLASH)
ON-CHIP
DEBUGGER
EEPROM
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
DATA
MEMORY
(SRAM)
CPU CORE
PORT A
8-BIT DATA BUS
PORT B
ISP
INTERFACE
DEBUG
INTERFACE
8-BIT
TIMER/COUNTER
TWO-WIRE
INTERFACE
TEMPERATURE
SENSOR
ANALOG
COMPARATOR
VOLTAGE
REFERENCE
16-BIT
TIMER/COUNTER
USART
MULTIPLEXER
ADC
PORT C
PORT D
PA[7:0]
PB[7:0]
PC[7:0]
PD[3:0]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
ATtiny828 [DATASHEET]
8371A–AVR–08/12
5
5 Page 
In the different addressing modes these address registers have functions as fixed displacement, automatic increment,
and automatic decrement (see the instruction set reference for details).
4.5 Stack Pointer
The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine
calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack grows from
higher memory locations to lower memory locations. This means that the PUSH instructions decreases and the POP
instruction increases the stack pointer value.
The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space
must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one
when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a
subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from
subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer
and the number of bits implemented is device dependent. In some AVR devices all data memory can be addressed using
SPL, only. In this case, the SPH register is not implemented.
The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of
SRAM. See Table 3 on page 17.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 7 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 7.
The Parallel Instruction Fetches and Instruction Executions
T1 T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 8 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two
register operands is executed, and the result is stored back to the destination register.
ATtiny828 [DATASHEET]
8371A–AVR–08/12
11
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