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29EE512 데이터시트 PDF




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29EE512 데이터시트, 핀배열, 회로
512 Kilobit (64K x8) Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for SST29EE512
– 3.0-3.6V for SST29LE512
– 2.7-3.6V for SST29VE512
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle
Time: 39 µs (typical)
Data Sheet
• Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm, 8mm x 20mm)
PRODUCT DESCRIPTION
The SST29EE512/29LE512/29VE512 are 64K x8
CMOS, Page-Write EEPROMs manufactured with
SST’s proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and
thick oxide tunneling injector attain better reliability
and manufacturability compared with alternate ap-
proaches. The SST29EE512/29LE512/29VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE512/29LE512/
29VE512 conform to JEDEC standard pinouts for byte-
wide memories.
Featuring high performance Page-Write, the
SST29EE512/29LE512/29VE512 provide a typical
Byte-Write time of 39 µsec. The entire memory, i.e., 64
KBytes, can be written page-by-page in as little as 2.5
seconds, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion
of a Write cycle. To protect against inadvertent write,
the SST29EE512/29LE512/29VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spec-
trum of applications, the SST29EE512/29LE512/
29VE512 are offered with a guaranteed Page-Write
endurance of 104 cycles. Data retention is rated at
greater than 100 years.
The SST29EE512/29LE512/29VE512 are suited for ap-
plications that require convenient and economical updat-
ing of program, configuration, or data memory. For all
system applications, the SST29EE512/29LE512/
29VE512 significantly improve performance and reliabil-
ity, while lowering power consumption. The
SST29EE512/29LE512/29VE512 improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
To meet high density, surface mount requirements, the
SST29EE512/29LE512/29VE512 are offered in 32-pin
TSOP (8mm x 14mm and 8mm x 20mm) and 32-lead
PLCC packages. A 600-mil, 32-pin PDIP package is also
available. See Figures 1 and 2 for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electri-
cal write capability. The SST29EE512/29LE512/
29VE512 do not require separate Erase and Program
operations. The internally timed Write cycle executes
both erase and program transparently to the user. The
SST29EE512/29LE512/29VE512 have industry stan-
dard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE512/
29LE512/29VE512 are compatible with industry stan-
dard EEPROM pinouts and functionality.
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© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
301-3 6/00
1
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.




29EE512 pdf, 반도체, 판매, 대치품
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE512/29LE512/29VE512 should
be programmed using the SDP command sequence. SST
recommends the SDP Disable Command Sequence not
be issued to the device prior to writing.
Please refer to the following Application Notes located at
the back of this databook for more information on using
SDP:
• Protecting Against Unintentional Writes When Using
Single Power Supply Flash Memories
• The Proper Use of JEDEC Standard Software Data
Protection
Product Identification
The product identification mode identifies the device as
the SST29EE512/29LE512/29VE512 and manufacturer
as SST. This mode may be accessed by hardware or
software operations. The hardware operation is typically
used by a programmer to identify the correct algorithm
for the SST29EE512/29LE512/29VE512. Users may
wish to use the software product identification operation
to identify the part (i.e., using the device code) when using
multiple manufacturers in the same socket. For details,
see Table 3 for hardware operation or Table 4 for software
operation, Figure 10 for the software ID entry and read
timing diagram and Figure 17 for the ID entry command
sequence flowchart. The manufacturer and device codes
are the same for both operations.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Byte
Data
Manufacturer’s ID
0000 H BF H
SST29EE512 Device ID
0001 H 5D H
SST29LE512 Device ID
0001 H 3D H
SST29VE512 Device ID
0001 H 3D H
Product Identification Mode Exit
301 PGM T1.1
In order to return to the standard read mode, the Soft-
ware Product Identification mode must be exited. Exiting
is accomplished by issuing the Software ID Exit (reset)
operation, which returns the device to the Read opera-
tion. The Reset operation may also be used to reset the
device to the Read mode after an inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g., not read correctly. See Table 4 for
software command codes, Figure 11 for timing wave-
form and Figure 17 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM OF SST29EE512/29LE512/29VE512
X-Decoder
A15 - A0
Address Buffer & Latches
CE#
OE#
WE#
Control Logic
524,288 Bit
EEPROM
Cell Array
Y-Decoder and Page Latches
I/O Buffers and Data Latches
DQ7 - DQ0
301 ILL B1.0
© 2000 Silicon Storage Technology, Inc.
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301-3 6/00

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29EE512 전자부품, 판매, 대치품
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
Output Short Circuit Current(1) ............................................................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
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SST29EE512 OPERATING RANGE
Range
Ambient Temp
Commercial 0°C to +70°C
Industrial
-40°C to +85°C
SST29LE512 OPERATING RANGE
Range
Ambient Temp
Commercial 0°C to +70°C
Industrial
-40°C to +85°C
SST29VE512 OPERATING RANGE
Range
Ambient Temp
Commercial 0°C to +70°C
Industrial
-40°C to +85°C
VCC
5V±10%
5V±10%
VCC
3.0V to 3.6V
3.0V to 3.6V
VCC
2.7V to 3.6V
2.7V to 3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time ......... 10 ns
Output Load ..................... 1 TTL Gate and CL = 100 pF
See Figures 12 and 13
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© 2000 Silicon Storage Technology, Inc.
7
301-3 6/00

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