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BU9799KV PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BU9799KV
기능 Standard LCD Segment Driver
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BU9799KV 데이터시트, 핀배열, 회로
Datasheet
Standard LCD Segment Driver
BU9799KV MAX 200 segments (SEG50×COM4)
Features
„ Integrated RAM for display data (DDRAM):
50 x 4 bit (Max 200 Segment)
„ LCD drive output :
4 Common output, 50 Segment output
„ Integrated Buffer AMP for LCD driving
„ Integrated Oscillator circuit
„ No external components
„ Low power consumption design
„ Independent power supply for LCD driving
„ Integrated Electrical volume register (EVR) function
Key Specifications
Supply Voltage Range:
+2.5V to +5.5V
LCD drive power supply Range: +2.5V to +5.5V
Operating Temperature Range: -40°C to +85°C
Max Segments:
200 Segments
Display Duty:
1/4
Bias:
1/2, 1/3 selectable
Interface:
2wire serial interface
Package
W (Typ.) x D (Typ.) x H (Max.)
Applications
„ Telephone
„ FAX
„ Portable equipment (POS, ECR, PDA etc.)
„ DSC
„ DVC
„ Car audio
„ Home electrical appliances
„ Meter equipment, etc.
VQFP64
12.00mm x 12.00mm x 1.60mm
Typical Application Circuit
VLCD
VDD
VDD
VLCD
Controller
VDD
SD
SCL
INHb
OSCIN
TEST1
TEST2
TEST3
VSS
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG49
Segment
LCD
Internal oscillator circuit mode
Figure 1. Typical application circuit
Product structureSilicon monolithic integrated circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product is not designed for protection against radioactive rays.
1/24
TSZ02201-0A0A2D300040-1-2
8.Jan.2013 Rev.002




BU9799KV pdf, 반도체, 판매, 대치품
BU9799KV MAX 200 segments (SEG50×COM4)
Datasheet
SDA
SCL
SDA
tBUF
tS LW
tf
tSCYC
tHD; STA tr
tSDH tS HW tSDS
tSU; STA
tSU; STO
Figure 4. Interface Timing
I/O equivalent circuit
VDD
VSS
VLCD
VSS
VDD
OSCIN
VSS
VLCD
SEG/COM
VSS
SDA
VSS
SCL
VSS
VDD
TEST3
VSS
Figure 5. I/O equivalent circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
4/24
TSZ02201-0A0A2D300040-1-2
8.Jan.2013 Rev.002

4페이지










BU9799KV 전자부품, 판매, 대치품
BU9799KV MAX 200 segments (SEG50×COM4)
Datasheet
Command transfer method
Issue Slave Address (“01111100”) after generation of “START condition”.
1byte after Slave Address always becomes command input.
MSB (“command or data judge bit”) of command decide if next data is command or display data.
When set “command or data judge bit”=‘1’, next byte data is command.
When set “command or data judge bit”=‘0’, next byte data is display data.
S Slave address A 1 Command A 1 Command A 1 Command A 0 Command A Display Data … P
When display data is transferred, inputting of command is not allowed
When one wants to input command again, please generate “START condition” once.
If “START condition” or “STOP condition” are inputted in the middle of command transmission, command will be
canceled.
If Slave address is inputted after “START condition”, execution of command is allowed.
Please input “Slave Address” in the first data transmission after “START condition”.
When Slave Address cannot be recognized in the first data transmission, Acknowledge does not return and next
transmission will be invalid. When data transmission is invalid status, if “START conditions” are transmitted again, it will
return to valid status.
Take care to observe MPU Interface characteristic such as Input rise time and Setup/Hold time when transferring
command and data (Refer to MPU Interface).
Write display and transfer method
This device has Display Data RAM (DDRAM) of 50×4=200bits.
The relationship between data input and display data, DDRAM data and address are as follows;
Slave address
Command
S 01111100 A 0 0000000 A a b c d e f g h A i j k l m n o p
A…P
Display Data
8 bit data will be stored in DDRAM. The address to be written is the address specified by ADSET command, and the
address is automatically incremented in every 4bit data.
Data can be continuously written in DDRAM by transmitting Data continuously.
(When RAM data is written successively after writing RAM data to 31h (SEG49), the address is returned to 00h (SEG0)
by the auto-increment function.
DDRAM address
00 01 02 03 04 05 06 07 ・・・ 2Fh 30h 31h
0a
e
i
m
COM0
1b
f
jn
BIT
2c g k o
COM1
COM2
3d
h
l
p
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
COM3
SEG47 SEG48 SEG49
Data transfer to DDRAM happens every 4bit data.
So it will be finished to transfer with no need to wait ACK.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
7/24
TSZ02201-0A0A2D300040-1-2
8.Jan.2013 Rev.002

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BU9799KV

Standard LCD Segment Driver

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