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C8051F520A-IM 데이터시트 PDF




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부품번호 C8051F520A-IM 기능
기능 8/4/2 kB ISP Flash MCU
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C8051F520A-IM 데이터시트, 핀배열, 회로
Analog Peripherals
- 12-Bit ADC
Programmable throughput up to 200 ksps
Up to 6/16 external inputs
Data dependent windowed interrupt generator
Built-in temperature sensor
- Comparator
Programmable hysteresis and response time
Configurable as wake-up or reset source
Low current
- POR/Brownout Detector
- Voltage Reference—1.5 and 2.2 V
(programmable)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Supply Voltage 2.0 to 5.25 V
- Built-in LDO regulator
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with
25 MHz system clock
- Expanded interrupt handler
C8051F52x/F53x
8/4/2 kB ISP Flash MCU Family
Memory
- 8/4/2 kB Flash; In-system byte programmable in
512 byte sectors
- 256 bytes internal data RAM
Digital Peripherals
- 16/6 port I/O; push-pull or open-drain, 5 V tolerant
- Hardware SPI™, and UART serial port
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Three general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
Clock Sources
- Internal oscillators: 24.5 MHz ±0.5% accuracy sup-
ports UART and LIN-Master operation
- External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly
Packages
- 10-Pin DFN (3 x 3 mm)
- 20-pin QFN (4 x 4 mm)
- 20-pin TSSOP
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
Rev. 1.4 4/12
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
+
-
TEMP
SENSOR
VOLTAGE
COMPARATOR
VREF VREG
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
Port 1
LIN
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Copyright © 2012 by Silicon Laboratories
C8051F52x/F53x




C8051F520A-IM pdf, 반도체, 판매, 대치품
C8051F52x/F52xA/F53x/F53xA
8.3.2. Stop Mode................................................................................................. 90
8.3.3. Suspend Mode .......................................................................................... 90
9. Memory Organization and SFRs............................................................................. 92
9.1. Program Memory............................................................................................... 92
9.2. Data Memory ..................................................................................................... 93
9.3. General Purpose Registers ............................................................................... 93
9.4. Bit Addressable Locations ................................................................................. 93
9.5. Stack ............................................................................................................ 93
9.6. Special Function Registers................................................................................ 93
10. Interrupt Handler.................................................................................................... 98
10.1. MCU Interrupt Sources and Vectors................................................................ 98
10.2. Interrupt Priorities ............................................................................................ 98
10.3. Interrupt Latency.............................................................................................. 98
10.4. Interrupt Register Descriptions ...................................................................... 100
10.5. External Interrupts ......................................................................................... 104
11. Reset Sources ...................................................................................................... 106
11.1. Power-On Reset ............................................................................................ 107
11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1) .................. 108
11.2.1. VDD Monitor Thresholds and Minimum VDD........................................ 108
11.3. External Reset ............................................................................................... 110
11.4. Missing Clock Detector Reset ....................................................................... 110
11.5. Comparator Reset ......................................................................................... 110
11.6. PCA Watchdog Timer Reset ......................................................................... 110
11.7. Flash Error Reset .......................................................................................... 110
11.8. Software Reset .............................................................................................. 111
12. Flash Memory....................................................................................................... 113
12.1. Programming The Flash Memory .................................................................. 113
12.1.1. Flash Lock and Key Functions .............................................................. 113
12.1.2. Flash Erase Procedure ......................................................................... 114
12.1.3. Flash Write Procedure .......................................................................... 114
12.2. Flash Write and Erase Guidelines ................................................................. 115
12.2.1. VDD Maintenance and the VDD monitor ................................................ 115
12.2.2. PSWE Maintenance .............................................................................. 115
12.2.3. System Clock ........................................................................................ 116
12.3. Non-volatile Data Storage ............................................................................. 117
12.4. Security Options ............................................................................................ 117
13. Port Input/Output ................................................................................................. 120
13.1. Priority Crossbar Decoder ............................................................................. 122
13.2. Port I/O Initialization ...................................................................................... 126
13.3. General Purpose Port I/O .............................................................................. 128
14. Oscillators ............................................................................................................ 135
14.1. Programmable Internal Oscillator .................................................................. 135
14.1.1. Internal Oscillator Suspend Mode ......................................................... 136
14.2. External Oscillator Drive Circuit..................................................................... 139
14.2.1. Clocking Timers Directly Through the External Oscillator..................... 139
4 Rev. 1.4

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C8051F520A-IM 전자부품, 판매, 대치품
C8051F52x/F52xA/F53x/F53xA
List of Figures
Figure 1.1. C8051F53xA/F53x-C Block Diagram .................................................... 16
Figure 1.2. C8051F52xA/F52x-C Block Diagram .................................................... 16
Figure 1.3. C8051F53x Block Diagram (Silicon Revision A) ................................... 17
Figure 1.4. C8051F52x Block Diagram (Silicon Revision A) ................................... 17
Figure 1.5. Development/In-System Debug Diagram .............................................. 19
Figure 1.6. Memory Map ......................................................................................... 20
Figure 1.7. 12-Bit ADC Block Diagram .................................................................... 22
Figure 1.8. Comparator Block Diagram ................................................................... 23
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 24
Figure 3.1. DFN-10 Pinout Diagram (Top View) ...................................................... 35
Figure 3.2. DFN-10 Package Diagram .................................................................... 38
Figure 3.3. DFN-10 Landing Diagram ..................................................................... 39
Figure 3.4. TSSOP-20 Pinout Diagram (Top View) ................................................. 40
Figure 3.5. TSSOP-20 Package Diagram ............................................................... 43
Figure 3.6. TSSOP-20 Landing Diagram ................................................................. 44
Figure 3.7. QFN-20 Pinout Diagram (Top View) ..................................................... 45
Figure 3.8. QFN-20 Package Diagram* ................................................................... 48
Figure 3.9. QFN-20 Landing Diagram* .................................................................... 50
Figure 4.1. ADC0 Functional Block Diagram ........................................................... 52
Figure 4.2. Typical Temperature Sensor Transfer Function .................................... 53
Figure 4.3. ADC0 Tracking Modes .......................................................................... 55
Figure 4.4. 12-Bit ADC Tracking Mode Example ..................................................... 56
Figure 4.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4 .............. 58
Figure 4.6. ADC0 Equivalent Input Circuits ............................................................. 60
Figure 4.7. ADC Window Compare Example:
Right-Justified Single-Ended Data ........................................................ 71
Figure 4.8. ADC Window Compare Example:
Left-Justified Single-Ended Data .......................................................... 71
Figure 5.1. Voltage Reference Functional Block Diagram ....................................... 72
Figure 6.1. External Capacitors for Voltage Regulator Input/Output ....................... 74
Figure 7.1. Comparator Functional Block Diagram ................................................. 76
Figure 7.2. Comparator Hysteresis Plot .................................................................. 77
Figure 8.1. CIP-51 Block Diagram ........................................................................... 81
Figure 9.1. Memory Map ......................................................................................... 92
Figure 11.1. Reset Sources ................................................................................... 106
Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 107
Figure 12.1. Flash Program Memory Map ............................................................. 117
Figure 13.1. Port I/O Functional Block Diagram .................................................... 120
Figure 13.2. Port I/O Cell Block Diagram .............................................................. 121
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped
(TSSOP 20 and QFN 20) .................................................................. 122
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
(TSSOP 20 and QFN 20) .................................................................. 123
Rev. 1.4
7

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부품번호상세설명 및 기능제조사
C8051F520A-IM

8/4/2 kB ISP Flash MCU

Silicon Laboratories
Silicon Laboratories

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