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PDF HX8345-A Data sheet ( Hoja de datos )

Número de pieza HX8345-A
Descripción TFT controller driver
Fabricantes Himax　
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( DOC No. HX8345-A-DS )
HX8345-A
128RGB x 160dot, 262k color, with
internal RAM, TFT controller driver
Preliminary Version 01 Sep., 2006

1 page




HX8345-A pdf
HX8345-A
128RGB x 160dot, 262k color, with
internal RAM, TFT controller driver
List of Figures
Sep., 2006
Figure 6. 1 80 System interface mode................................................................................................ 83
Figure 6. 2 Index Register.................................................................................................................. 84
Figure 6. 3 Status Read Register ....................................................................................................... 84
Figure 6. 4 Start Oscillation Register (R00h) ...................................................................................... 84
Figure 6. 5 Driver Output Control Register (R01h) .............................................................................. 84
Figure 6. 6 LCD-Driving-Waveform Control Register (R02h)............................................................... 85
Figure 6. 7 Power Control Register 1 (R03h)...................................................................................... 86
Figure 6. 8 Different Connection of C22 Capacitor.............................................................................. 87
Figure 6. 9 Entry Mode Register (R05h) ............................................................................................. 88
Figure 6. 10 Address Direction Settings ............................................................................................. 89
Figure 6. 11 16-bit Compare Register (R06h) ..................................................................................... 90
Figure 6. 12 Display Control Register 1 (R07h) .................................................................................. 90
Figure 6. 13 Display Control Register 2 (R08h) .................................................................................. 93
Figure 6. 14 BP/FP ............................................................................................................................ 95
Figure 6. 15 Power Control Register 2 (R09h).................................................................................... 96
Figure 6. 16 External Display Interface Control Register 1 (R0Ah)...................................................... 97
Figure 6. 17 The setting of DFM and TRI (1) ...................................................................................... 99
Figure 6. 18 The setting of DFM and TRI (2) .................................................................................... 100
Figure 6. 19 Frame Cycle Control Register (R0Bh)........................................................................... 100
Figure 6. 20 Equalized Period and Source Output Delay .................................................................. 102
Figure 6. 21 Non-overlap Time between Two Adjacent Gate Output Pulse........................................ 102
Figure 6. 22 Power Control Register 2 (R0Ch) ................................................................................. 103
Figure 6. 23 Power Control Register 3 (R0Dh) ................................................................................. 103
Figure 6. 24 Power Control Register 4 (R0Eh).................................................................................. 104
Figure 6. 25 Gate Scan Position Register (R0Fh)............................................................................. 106
Figure 6. 26 SCN bits and Scanning Start Position for Gate Driver ................................................... 107
Figure 6. 27 CP/WM 18/16-bit Selection Register (R10h) ................................................................. 107
Figure 6. 28 Vertical Scroll Control Register (R11h).......................................................................... 108
Figure 6. 29 First Screen Driving Position Register (R14h) ............................................................... 108
Figure 6. 30 Second Screen Driving Position Register (R15h) .......................................................... 109
Figure 6. 31 Horizontal RAM Address Position Register (R44h)........................................................ 109
Figure 6. 32 Vertical RAM Address Position Register (R45h) .............................................................110
Figure 6. 33 Window Address Setting Range ....................................................................................110
Figure 6. 34 16-bit RAM Write Data Mask Register (R20h) ................................................................110
Figure 6. 35 RAM Address Register (R21h)....................................................................................... 111
Figure 6. 36 Write Data Register (R22h) ........................................................................................... 111
Figure 6. 37 Bit Mapping of One Pixel Data: Input Data (18-bit Interface) Written to GRAM through ..112
Figure 6. 38 Bit Mapping of One Pixel Data: Input Data (16-bit Interface) Written to GRAM through ..112
Figure 6. 39 Bit Mapping of One Pixel Data: Input Data (9-bit Interface) Written to GRAM through Write
..................................................................................................................................................113
Figure 6. 40 Bit Mapping of One Pixel Data: Input Data (8-bit Interface) Written to GRAM through Write
..................................................................................................................................................114
Figure 6. 41 Bit Mapping of One Pixel Data: Input Data (Serial Data Transfer interface) Written to ....115
Figure 6. 42 Bit Mapping of One Pixel Data: Input Data (18/16/6-bit RGB Interface) Written to GRAM
..................................................................................................................................................116
Figure 6. 43 Read Data Register (R22h) ...........................................................................................117
Figure 6. 44 Output Data Read from GRAM through Read Data Register in 18-bit Interface Mode ....117
Figure 6. 45 Output Data Read from GRAM through Read Data Register in 16- /9- /8-bit Interface ....118
Figure 6. 46 Flow Chart of GRAM Read Data....................................................................................119
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.Subject to change without notice.
-P.3-
Sep., 2006

5 Page





HX8345-A arduino
HX8345-A
128RGBx160 dots, 262,144 color TFT controller driver
3. Device Overview
3.1 Block Diagram
IOVCC
GND
IM3~1,
IM0/ID
NCS
RS
E_NWR
RW_NRD
SDI
SDO
SCL
DB/PD17~0
VSYNC
DOTCLK
NRESET
TEST1
TEST2
TS7~0
VCC
Index Register
(IR)
7 18
Control
Register
(CR)
Address Counter
System_IF
(AC)
-18-bit
-16-bit
-9-bit
-8-bit
16
18
-Serial
18
RGB_IF
-18-bit
Read data
18 latch
Write data
latch
-16-bit
-6-bit
-Vsync 18 72
Power
Regulator
VDDD
Graphic RAM
(GRAM)
46,080 bytes
OSC2
OSC1
Timing
generator
VSSD
VSSA
DCTEST
LCD driving power
circuit
DATA SHEET Preliminary V01
S384~1
Source
driver
M/AC
circuit
Latch
circuit
V0~63
Grayscale voltage
generator
VGS
VTEST
VMON
Gamma adjusting
circuit
G1~G160
VGH/VGL
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.Subject to change without notice.
-P.9-
Sep., 2006

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