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90LV019 데이터시트 PDF




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기능 DS90LV019
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90LV019 데이터시트, 핀배열, 회로
August 2000
DS90LV019
3.3V or 5V LVDS Driver/Receiver
General Description
The DS90LV019 is a Driver/Receiver designed specifically
for the high speed low power point-to-point interconnect ap-
plications. The device operates from a single 3.3V or 5.0V
power supply and includes one differential line driver and
one receiver. The DS90LV019 features an independent
driver and receiver with TTL/CMOS compatibility (DIN and
ROUT). The logic interface provides maximum flexibility as 4
separate lines are provided (DIN, DE, RE, and ROUT). The
device also features a flow-through pin out which allows
easy PCB routing for short stubs between its pins and the
connector. The driver has 3.5 mA output loop current.
The driver translates between TTL levels (single-ended) to
Low Voltage Differential Signaling levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common-mode noise rejection.
The receiver threshold is ±100 mV over a ±1V common-
mode range and translates the low swing differential levels
to standard (TTL/CMOS) levels.
Features
n LVDS Signaling
n 3.3V or 5.0V operation
n Low power CMOS design
n Balanced Output Impedance
n Glitch free power up/down (Driver disabled)
n High Signaling Rate Capacity (above 100 Mbps)
n Ultra Low Power Dissipation
n ±1V Common-Mode Range
n ±100 mV Receiver Sensitivity
n Product offered in SOIC and TSSOP packages
n Flow-Through Pin Out
n Industrial Temperature Range Operation
Connection Diagram
Block Diagram
DS100053-1
Order Number DS90LV019TM or DS90LV019TMTC
See NS Package Number M14A or MTC14
DS100053-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100053
www.national.com




90LV019 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics (Continued)
TA = −40˚C to +85˚C, VCC = 3.3V ± 0.3V. (Note 6)
Symbol
Parameter
DRIVER TIMING REQUIREMENTS
tPHZ Disable Time High to Z
tPLZ Disable Time Low to Z
tPZH Enable Time Z to High
tPZL Enable Time Z to Low
RECEIVER TIMING REQUIREMENTS
tPHLD
tPLHD
tSKD
tr
tf
tPHZ
tPLZ
tPZH
tPZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |tPHLD − tPLHD|
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Conditions
Min Typ Max Units
RL = 100,
1.5 4.0 8.0
CL = 10 pF
2.5 5.3 9.0
(Figure 4 and Figure 5)
4.0
6.0
8.0
3.5 6.0 8.0
ns
ns
ns
ns
CL = 10 pF,
VID = 200 mV
(Figure 6 and Figure 7)
RL = 500,
CL = 10 pF
(Figure 8 and Figure 9)
3.0
3.0
0.15
0.15
3.0
3.0
3.0
3.0
5.8
5.6
0.55
2.0
0.9
4.0
4.5
6.0
6.0
7.0
9.0
1.5
3.0
3.0
6.0
6.0
8.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC Electrical Characteristics
TA = −40˚C to +85˚C, VCC = 5.0V ± 0.5V. (Note 6)
Symbol
Parameter
Conditions
Min Typ Max Units
DRIVER TIMING REQUIREMENTS
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
tSKD
Differential Skew |tPHLD − tPLHD|
tTLH Transition Time Low to High
tTHL Transition Time High to Low
tPHZ Disable Time High to Z
tPLZ Disable Time Low to Z
tPZH Enable Time Z to High
tPZL Enable Time Z to Low
RECEIVER TIMING REQUIREMENTS
RL = 100,
CL = 10 pF
(Figure 2 and Figure 3)
RL = 100,
CL = 10 pF
(Figure 4 and Figure 5)
2.0
1.0
0.15
0.15
1.5
3.0
2.0
2.0
3.3
3.3
0.6
0.9
1.2
3.5
5.2
4.5
4.5
6.0
5.0
1.0
3.0
3.0
7.0
9.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHLD
tPLHD
tSKD
tr
tf
tPHZ
tPLZ
tPZH
tPZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |tPHLD − tPLHD|
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
CL = 10 pF,
VID = 200 mV
(Figure 6 and Figure 7)
RL = 500,
CL = 10 pF
(Figure 8 and Figure 9)
3.0
3.0
0.15
0.15
3.0
3.5
3.0
3.0
6.0
5.6
0.7
0.8
0.8
3.5
3.6
5.0
5.0
8.0
8.0
1.6
3.0
3.0
4.5
7.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.national.com
4

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90LV019 전자부품, 판매, 대치품
Test Circuits and Timing Waveforms (Continued)
DS100053-11
FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms
DS100053-13
FIGURE 10. Terminated Input Fail-Safe Circuit
Typical Application Diagram
Applications Information
The DS90LV019 has two control pins, which allows the de-
vice to operate as a driver, a receiver or both driver and a re-
ceiver at the same time. There are a few common practices
which should be implied when designing PCB for LVDS sig-
naling. Recommended practices are:
Use at least 4 PCB board layer (LVDS signals, ground,
power and TTL signals).
Keep drivers and receivers as close to the (LVDS port
side) connector as possible.
Bypass each LVDS device and also use distributed bulk
capacitance. Surface mount capacitors placed close to
power and ground pins work best. Two or three multi-
layer ceramic (MLC) surface mount capacitors 0.1 µF,
DS100053-12
and 0.01 µF in parallel should be used between each VCC
and ground. The capacitors should be as close as pos-
sible to the VCC pin.
Use controlled impedance traces which match the differ-
ential impedance of your transmission medium (i.e.,
Cable) and termination resistor.
Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
Isolate TTL signals from LVDS signals.
MEDIA (CABLE AND CONNECTOR) SELECTION:
Use controlled impedance media. The cables and con-
nectors should have a matched differential impedance of
about 100.
7 www.national.com

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