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PDF ADXL313 Data sheet ( Hoja de datos )

Número de pieza ADXL313
Descripción Digital Accelerometer
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
3-Axis, ±0.5 g/±1 g/±2 g/±4 g
Digital Accelerometer
ADXL313
FEATURES
GENERAL DESCRIPTION
Ultralow power (scales automatically with data rate)
The ADXL313 is a small, thin, low power, 3-axis accelerometer
As low as 30 µA in measurement mode (VS = 3.3 V)
with high resolution (13-bit) measurement up to ±4 g. Digital
As low as 0.1 µA in standby mode (VS = 3.3 V)
output data is formatted as 16-bit twos complement and is
Low noise performance
accessible through either a serial port interface (SPI) (3-wire or
150 μg/√Hz typical for X- and Y-axes
4-wire) or I2C digital interface.
250 μg/√Hz typical for the Z-axis
Embedded, patent pending FIFO technology minimizes host
processor load
User-selectable resolution
Fixed 10-bit resolution for any g range
Fixed 1024 LSB/g sensitivity for any g range
Resolution scales from 10-bit at ±0.5 g to 13-bit at ±4 g
Built-in motion detection functions for activity/inactivity
monitoring
Supply and I/O voltage range: 2.0 V to 3.6 V
SPI (3-wire and 4-wire) and I2C digital interfaces
Flexible interrupt modes mappable to two interrupt pins
Measurement range selectable via serial command
Bandwidth selectable via serial command
Wide temperature range (−40°C to +105°C)
The ADXL313 is well suited for car alarm or black box applications.
It measures the static acceleration of gravity in tilt-sensing applica-
tions, as well as dynamic acceleration resulting from motion or
shock. Its high resolution (1024 LSB/g) and low noise (150 μg/√Hz)
enable resolution of inclination changes of as little as 0.1°. A built-
in FIFO facilitates using oversampling techniques to improve
resolution to as little as 0.025° of inclination.
Several built-in sensing functions are provided. Activity and
inactivity sensing detects the presence or absence of motion and
whether the acceleration on any axis exceeds a user-set level.
These functions can be mapped to interrupt output pins. An
integrated 32-level FIFO can be used to store data to minimize
host processor intervention, resulting in reduced system power
consumption.
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 5 mm × 5 mm × 1.45 mm LFCSP package
Qualified for automotive applications
APPLICATIONS
Low power modes enable intelligent motion-based power
management with threshold sensing and active acceleration
measurement at extremely low power dissipation.
The ADXL313 is supplied in a small, thin 5 mm × 5 mm ×
1.45 mm, 32-lead LFCSP package and is pin compatible with
Car alarms
the ADXL312 accelerometer device.
Hill start aid (HSA) systems
Electronic parking brakes
Data recorders (black boxes)
FUNCTIONAL BLOCK DIAGRAM
VS VDD I/O
ADXL313
POWER
MANAGEMENT
3-AXIS
SENSOR
SENSE
ELECTRONICS
ADC
DIGITAL
FILTER
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
32-LEVEL
FIFO
SERIAL I/O
SDA/SDI/SDIO
SDO/ALT
ADDRESS
SCL/SCLK
GND
CS
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADXL313 pdf
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADXL313
GND 1
RESERVED 2
GND 3
GND 4
VS 5
CS 6
RESERVED 7
NC 8
ADXL313
TOP VIEW
(Not to Scale)
24 SDA/SDI/SDIO
23 SDO/ALT ADDRESS
22 RESERVED
21 INT2
20 INT1
19 NC
18 NC
17 NC
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1 GND
2 RESERVED
3 GND
4 GND
5 VS
6 CS
7 RESERVED
8 to 19
NC
20 INT1
21 INT2
22 RESERVED
23 SDO/ALT ADDRESS
24 SDA/SDI/SDIO
25 NC
26 SCL/SCLK
27 to 30
NC
31 VDD I/O
32 NC
EP
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE.
Figure 2. Pin Configuration
Description
This pin must be connected to ground.
Reserved. This pin must be connected to VS or left open.
This pin must be connected to ground.
This pin must be connected to ground.
Supply Voltage.
Chip Select.
Reserved. This pin must be left open.
No Connect. Do not connect to this pin.
Interrupt 1 Output.
Interrupt 2 Output.
Reserved. This pin must be connected to GND or left open.
Serial Data Output/Alternate I2C Address Select.
Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input/Output (SPI 3-Wire).
No Connect. Do not connect to this pin.
I2C Serial Communications Clock/SPI Serial Communications Clock.
No Connect. Do not connect to this pin.
Digital Interface Supply Voltage.
No Connect. Do not connect to this pin.
Exposed Pad. The exposed pad must be soldered to the ground plane.
Rev. 0 | Page 5 of 28

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ADXL313 arduino
Data Sheet
ADXL313
Table 8. SPI Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
Low Level Output Current (IOL)
High Level Output Current (IOH)
Pin Capacitance
Test Conditions/Comments
VIN = VDD I/O
VIN = 0 V
IOL = 10 mA
IOH = −4 mA
VOL = VOL, max
VOH = VOH, min
fIN = 1 MHz, VIN = 2.5 V
Limit1
Min Max
0.7 × VDD I/O
−0.1
0.3 × VDD I/O
0.1
0.8 × VDD I/O
10
0.2 × VDD I/O
−4
8
Unit
V
V
µA
µA
V
V
mA
mA
pF
1 Limits based on characterization results; not production tested.
Table 9. SPI Timing (TA = 25°C, VS = VDD I/O = 3.3 V)1
Limit2, 3
Parameter Min
Max Unit Description
fSCLK 5 MHz SPI clock frequency.
tSCLK
200
ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40.
tDELAY
5
ns CS falling edge to SCLK falling edge.
tQUIET
5
ns SCLK rising edge to CS rising edge.
tDIS 10 ns CS rising edge to SDO disabled.
tCS,DIS
150
ns CS deassertion between SPI communications.
tS 0.3 × tSCLK
ns SCLK low pulse width (space).
tM 0.3 × tSCLK
ns SCLK high pulse width (mark).
tSETUP
5
ns SDI valid before SCLK rising edge.
tHOLD
5
ns SDI valid after SCLK rising edge.
tSDO 40 ns SCLK falling edge to SDO/SDIO output transition.
tR4 20 ns SDO/SDIO output high to output low transition.
tF4 20 ns SDO/SDIO output low to output high transition.
1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2 Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 8.
4 Output rise and fall times measured with capacitive load of 150 pF.
Rev. 0 | Page 11 of 28

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