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PDF BL8509B Data sheet ( Hoja de datos )

Número de pieza BL8509B
Descripción Ultra-small package High-precision Voltage Detector
Fabricantes BELLING 
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BL8509B
Ultra-small package High-precision Voltage Detector with delay
circuit, BL8509B Series
General Description
BL8509B Series is a series of high-precision voltage
detectors with a built-in delay time generator of fixed
time developed using CMOS process. Internal
oscillator and counter timer can delay the release
signal without external parts. Detect voltage is
extremely accurate with minimal temperature drift.
CMOS output configurations are available.
Features
Highly accuracy±2%
Low power consumptionTYP 0.9uA (VDD=3V)
Detect voltage range1.0V~6.5V in 0.1V increments
Operating voltage range0.7V~7V
Detect voltage temperature characteristics
TYP±100ppm/
Output configurationCMOS
PackageSOT-23SOT-23-3SOT-23-5
Selection Guide
BL8509B- XXX X X XX
Page1
Typical Application
Package type
RMSOT-23-3
RNSOT-23-5
ROSOT-23
Output type
NNch
CCMOS
Delay time
A50mS
B100mS
C150mS
D200mS
E250mS
F300mS
G400mS
Power monitor for portable equipment such as
notebook computers, digital still cameras, PDA, and
cellular phones
Constant voltage power monitor for cameras, video
equipment and communication devices.
Power monitor for microcomputers and reset for
CPUs.
System battery life and charge voltage monitors
Typical Application Circuit
Detector voltage
090……0.9V
100……1.0V
263……2.63V
300……3.0V
465……4.65V
……
600……6.0V
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BL8509B pdf
BL8509B
Functional Description
1. Basic Operation: CMOS Output (Active Low)
1-1. When the power supply voltage (VDD) is higher than the release voltage (+VDET), the Nch transistor is OFF and
the Pch transistor is ON to provide VDD (high) at the output. Since the Nch transistor N1 in Figure 1 is OFF, the
(
R
B
+
R
C
)
VDD
comparator input voltage is
R
A
+
R
B
+
R
C
.
1-2. When the VDD goes below +VDET, the output provides the VDD level, as long as VDD remains above the
detection voltage (–VDET). When the VDD falls below –VDET (point A in Figure 2), the Nch transistor
becomes ON, the Pch transistor becomes OFF, and the VSS level appears at the output. At this time the Nch
R
B
VDD
transistor N1 in Figure 1 becomes ON, the comparator input voltage is changed to
R
A
+
R
B
.
1-3. When the VDD falls below the minimum operating voltage, the output becomes undefined, or goes to VDD when
the output is pulled up to VDD.
1-4. The VSS level appears when VDD rises above the minimum operating voltage. The VSS level still appears
even when VDD surpasses the –VDET, as long as it does not exceed the release voltage +VDET.
1-5. When VDD rises above +VDET (point B in Figure 2), the Nch transistor becomes OFF and the Pch transistor
becomes ON to provide VDD at the output. The VDD at the OUT pin is delayed for Td due to the delay circuit.
2. Delay Circuit
2-1. Delay Time
The delay circuit delays the output signal from the time at which the power voltage (VDD) exceeds the release
voltage (+VDET) when VDD is turned on. The output signal is not delayed when the VDD goes below the
detection voltage (–VDET). (Refer to Figure 2.) The delay time (tD) is a fixed value that is determined by a built-in
oscillation circuit and counter.
2-2. DS Pin (ON/OFF Switch Pin for Delay Time)
The DS pin should be connected to Low or High. When the DS pin is High, the output delay time becomes
short since the output signal is taken from the middle of counter circuit (Refer to Figure 3).
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