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PDF TL0324S Data sheet ( Hoja de datos )
| Número de pieza | TL0324S | |
| Descripción | 65COM / 132SEG DRIVER & CONTROLLER | |
| Fabricantes | TOMATO | |
| Logotipo |  |
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LCD driver IC
April. 2004
VER 0.2
TL0324S
65COM / 132SEG DRIVER & CONTROLLER
FOR STN LCD
TOMATO LSI Inc.
1 page  
TL0324S
Ver 0.1
65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD
4. PIN DESCRIPTION
Table 4-1. Pin description
Power supply
Name
I/O
Description
VDD
VSS
V0
V1
V2
V3
V4
Power
supply
Shared with the MPU power supply terminal VCC.
This is a 0V terminal connected to the system GND.
Main VSS pad (PAD No. 43,44,45,46 and 47) have to be connected
The voltage is determined by the LCD pixel impedance-converted for application by an
operational amplifier.
Voltage have the following relationship: V0 >V1>V2>V3>V4>VSS(GND)
When the on-chip power circuit is active, these voltages are generated according
to the state of LCD bias, as shown in the table below.
LCD Bias
V1
V2
V3
V4
I/O
1/9 bias
(8/9) x V0
(7/9) x V0
(2/9) x V0
(1/9) x V0
1/8 bias
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/7 bias
(6/7) x V0
(5/7) x V0
(2/7) x V0
(1/7) x V0
1/6 bias
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/5 bias
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
LCD driver power supply
C1+ Capacitor1+ positive connection pin for the voltage converter
C1- Capacitor1- negative connection pin for voltage converter
C2+ Capacitor2+ positive connect ion pin for voltage converter
O
C2- Capacitor2- negative connection pin for voltage converter
C3+
C4+
VOUT
Capacitor3+ positive connection pin for voltage converter
Capacitor4+ positive connection pin for voltage converter
I/O
Voltage converter input / output pin
Connect this pin to VSS through capacitor.
VR
VCI
VEXT
REF
I V0 voltage adjustment pin. It is valid only when using external resistors.(INTRS=”L”)
This is the reference voltage for the voltage converter circuit for the LCD drive.
I Whether internal voltage converter use or not use, this pin should be fixed.
The voltage should have the following range: 2.4V ≤ VCI ≤ 3.6V
This is the externally input reference voltage (VREF) for the internal voltage regulator.
I It is valid only when external VREF is used (REF = “L”).
When using internal VREF, this pin is Open
Select the external VREF voltage via VEXT pin
I -REF = “L”: using the external VREF
-REF = “H”: using the internal VREF
TOMATO LSI Inc.
5
5 Page 
TL0324S
Ver 0.1
65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD
f. Data accessing
The TL0324S uses bus holder and internal data bus for data read and data write with the MPU.
When writing data from the MPU to on-chip RAM, the data is automatically transferred from the bus holder
to the on-chip RAM as shown in figure 5-2. When the MPU reads data from on-chip RAM, the first data
read cycle stores the data in the bus holder (dummy read) and the MPU reads this stored data from bus
holder for the next data read cycle as shown in figure 5-3. This means the data of the specified address
cannot be output with the read display data instruction right after the address sets, but can be output at the
second read of data. Therefore, a dummy read cycle must be inserted between each pair of address sets
when a sequence of address sets is executed.
RS
/WR
DB7
to DB0
N
D(N)
D(N+1)
D(N+2)
D(N+3)
D(N+4)
/WR
Bus
Holder
Column
Address
RS
/WR
/RD
DB7
to DB0
/WR
/RD
Bus
Holder
Column
Address
TOMATO LSI Inc.
N
D(N)
D(N+1)
D(N+2)
D(N+3)
D(N+4)
N
N+1 N+2
N+3 N+4
Figure 5-2. Write timing
N
Dummy
D(N)
D(N+1)
D(N+2)
D(N+3)
N
N
D(N)
N+1
D(N+1)
N+2
D(N+2)
N+3
Figure 5-3. Read timing
11
D(N+3)
N+4
D(N+4)
N+5
11 Page | ||
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