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PDF ATR0621P1 Data sheet ( Hoja de datos )
| Número de pieza | ATR0621P1 | |
| Descripción | GPS Baseband Processor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 16 Channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm
– Tracking Sensitivity: –150 dBm
• Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– EmbeddedICE™ (In-circuit Emulator)
• 128 Kbyte Internal RAM
• 384 Kbyte Internal ROM, Firmware Version V5.0
• Position Technology Provided by u-blox
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 8 Mbytes
– Up to 4 Chip Selects
– Software Programmable 8-bit/16-bit External Data Bus
• 6-channel Peripheral Data Controller (PDC)
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
• 32 User-programmable I/O Lines
• 1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 2.3V to 3.6V or 1.8V Core Supply Voltage
• Includes Power Supervisor
• 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
• 4 Kbytes Battery Backup Memory
• 9 mm × 9 mm 100-pin BGA Package (LFBGA100)
• RoHS-compliant
GPS Baseband
Processor
ATR0621P1
Automotive
Summary
NOTE: This is a summary document.
The complete document is available.
For more information, please contact
your local Atmel sales office.
4975BS–GPS–05/08
1 page  
ATR0621P1
3. Pin Configuration
3.1 Pinout
Figure 3-1.
Pinout LFBGA100 (Top View)
10
9
8
7
6
5
4
3
2
1
A B CDE F GH J K
ATR0621P1
Table 3-1. ATR0621P1 Pinout
Pin Name LFBGA100 Pin Type
Pull Resistor
(Reset Value)(1) Firmware Label
PIO Bank A
PIO Bank B
CLK23
G9
IN
DBG_EN
H4
IN
PD
EM_A1
A6
OUT
EM_A2
A5
OUT
EM_A3
A4
OUT
EM_A4
A2
OUT
EM_A5
A3
OUT
EM_A6
B5
OUT
EM_A7
B4
OUT
EM_A8
B2
OUT
EM_A9
D4
OUT
EM_A10
C2
OUT
EM_A11
D6
OUT
EM_A12
D7
OUT
EM_A13
C3
OUT
EM_A14
C1
OUT
EM_A15
D5
OUT
Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. VBAT18 represent the internal power supply of the backup power domain
3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup-
ply of 3.0V to 3.6V is required.
5. This pin is not connected
4975BS–GPS–05/08
5
5 Page 
3.3 External Connections for a Working GPS System
Figure 3-2. Example of an External Connection
ATR0601
SIGH
SIGL
SC
PuRF
PuXTO
NC
see Table 3-15
NC
SIGHI
SIGLO
CLK23
RF_ON
NSLEEP
NRESET
ATR0621P1
P8
P20
EM_DA0 - 15
EM_A1 - 19
USB_DM
USB_DP
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
NC
NC
NC
NC
NC
P0 - 7
P9 - 15
P16 - 17
P19
P23 - 30
TMS
TCK
TDI
NTRST
TDO
P31
P18
P22
P21
XT_IN
XT_OUT
NC DBG_EN
GND
+3V
(see Power Supply)
GND
+3V
(see Power Supply)
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
LDO_IN
LDOBAT_IN
VBAT18
VBAT
VDDIO
VDD_USB
NC: Not connected
ATR0621P1
STATUS LED
TIMEPULSE
Optional
USB
Optional
USART 1
Optional
USART 2
32.368 kHz
(see RTC)
+3V
(see Power Supply)
+3V
(see Power Supply)
4975BS–GPS–05/08
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ATR0621P1.PDF ] | |
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