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PDF KSZ8873MML Data sheet ( Hoja de datos )
| Número de pieza | KSZ8873MML | |
| Descripción | Integrated 3-Port 10/100 Managed Switch | |
| Fabricantes | Micrel Semiconductor | |
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KSZ8873MML
Integrated 3-Port 10/100 Managed Switch
with PHYs
Rev. 1.6
General Description
The KSZ8873MML are highly integrated 3-port switch on
a chip ICs in industry’s smallest footprint. It is designed
to enable a new generation of low port count, cost-
sensitive and power efficient 10/100Mbps switch
systems. Low power consumption, advanced power
management and sophisticated QoS features (e.g., IPv6
priority classification support) make these devices ideal
for IPTV, IP-STB, VoIP, automotive and industrial
applications.
The KSZ8873 family is designed to support the GREEN
requirement in today’s switch systems. Advanced power
management schemes include hardware power down,
software power down, per port power down and the
energy detect mode that shuts downs the transceiver
when a port is idle.
KSZ8873MML also offer a by-pass mode, which enables
system-level power saving. In this mode, the processor
connected to the switch through the MII interface can be
shut down without impacting the normal switch operation.
The configurations provided by the KSZ8873 family
enables the flexibility to meet requirements of different
applications:
• KSZ8873MML: One 10/100BASE-T/TX transceivers
and two MII interfaces.
The device is available in RoHS-compliant 64-pin LQFP
package. Industrial grade is also available.
The datasheets and supporting documents can be found
on Micrel’s web site at: www.micrel.com.
_________________________________________________________________________________________________________
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2011
M9999-092111-1.6
1 page  
Micrel, Inc.
KSZ8873MML
Configuration Interface ........................................................................................................................................ 35
Loopback Support................................................................................................................................................ 40
MII Management (MIIM) Registers ........................................................................................................................ 41
Memory Map (8-bit Registers)............................................................................................................................... 46
Global Registers .................................................................................................................................................. 46
Port Registers ...................................................................................................................................................... 46
Advanced Control Registers ................................................................................................................................ 46
Register Description .............................................................................................................................................. 47
Global Registers (Registers 0 – 15) .................................................................................................................... 47
Port Registers (Registers 16 – 95) ...................................................................................................................... 54
Advanced Control Registers (Registers 96-198) ................................................................................................. 64
Static MAC Address Table .................................................................................................................................... 78
VLAN Table ............................................................................................................................................................. 80
Dynamic MAC Address Table ............................................................................................................................... 81
MIB (Management Information Base) Counters.................................................................................................. 82
Additional MIB Counter Information.............................................................................................................. 85
Absolute Maximum Ratings(1) ...............................................................................................................................86
Operating Ratings(2) ............................................................................................................................................... 86
Electrical Characteristics(5) ................................................................................................................................... 86
EEPROM Timing ................................................................................................................................................. 88
MII Timing ............................................................................................................................................................ 89
I2C Slave Mode Timing ........................................................................................................................................ 91
SPI Timing ........................................................................................................................................................... 93
Auto-Negotiation Timing ...................................................................................................................................... 95
MDC/MDIO Timing .............................................................................................................................................. 96
Reset Timing........................................................................................................................................................ 97
Reset Circuit ........................................................................................................................................................ 98
Selection of Isolation Transformers..................................................................................................................... 99
Selection of Reference Crystal ............................................................................................................................. 99
Package Information............................................................................................................................................ 100
September 2011
5 M9999-092111-1.6
5 Page 
Micrel, Inc.
KSZ8873MML
Pin Description and I/O Assignment (Continued)
Pin Number
59
60
61
Pin Name
VDDCO
Type (1)
P
SMTXEN1
P1LED1
I
Ipu/O
Description
1.8V core power voltage output (internal 1.8V LDO regulator output),
this 1.8V output pin provides power to both VDDA_1.8 and VDDC
input pins.
Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not
connect an external power supply to VDDCO pin. The ferrite bead is
requested between analog and digital 1.8V core power.
Switch MII transmit enable
Port 1 LED Indicators: (Not used)
Strap option: Port 3 flow control selection(P3FFC)
PU = always enable (force) port 3 flow control feature
PD = disable
62
P1LED0
Ipd/O
Port 1 LED Indicators: (Not used)
Strap option: Port 3 duplex mode selection(P3DPX)
PU = port 3 set to half duplex mode
PD = port 3 set to full duplex mode (default)
September 2011
11 M9999-092111-1.6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8873MML.PDF ] | |
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