|
|
PDF KSZ9692PB Data sheet ( Hoja de datos )
| Número de pieza | KSZ9692PB | |
| Descripción | Integrated Gigabit Networking and Communications Controller | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de KSZ9692PB (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
KSZ9692PB, KSZ9692PB-S
Integrated Gigabit Networking and
Communications Controller
Rev. 5.0
General Description
The KSZ9692PB, KSZ9692PB-S is a highly integrated
System-on-Chip (SoC) containing an ARM 922T 32-bit
processor and a rich set of peripherals to address the cost-
sensitive, high-performance needs of a wide variety of high
bandwidth networking and communications applications.
The KSZ9692PB-S is a small package version of
KSZ9692PB and it supports 16 bit DDR data width.
Features
ARM 922T High-Performance Processor Core
• 250 MHz ARM 922T RISC processor core
• 8KB I-cache and 8KB D-cache
• Configurable Memory Management Unit (MMU) for
Linux and WinCE
Memory Controller
• 8/16-bit external bus interface for FLASH, ROM, SRAM,
and external I/O
• NAND FLASH controller with boot option
• 200MHz 32-bit DDR controller
• Two JEDEC Specification JESD82-1 compliant
differential clock drivers for a glueless DDR interface
solution
Ethernet Interfaces
• Two Gb (10/100/1000 Mbps) MACs
• MII or RGMII interface
• Fully compliant with IEEE 802.3 Ethernet standards
IP Security Engine
• Hardware IPSec Engine guarantees 100Mbps VPN
• Secure Socket Layer Support
• DES/3DES/AES/RC4 Cyphers
• MD-5, SHA-1, SHA-256 Hashing Algorithms
• HMAC
• SSLMAC
PCI Interface
• Version PCI 2.3
• 32-bit 33/66MHz
• Integrated PCI Arbiter supports three external masters
• Configurable as Host bridge or Guest device
• Glueless Support for mini-PCI or CardBus devices
Dual High-Speed USB 2.0 Interfaces
• Two USB2.0 ports with integrated PHY
• Can be configured as 2-port host, or host + device
SDIO/SD Host Controller
• Meets SD Host Controller Standard Specification
Version 1.0
• Meets SDIO card specification Version 1.0
DMA Controllers
• Dedicated DMA channels for PCI, USB, IPSec, SDIO
and Ethernet ports.
Peripherals
• Four high-speed UART ports up to 5 Mbps
• Two programmable 32-bit timers with watchdog timer
capability
• Interrupt Controller
• Twenty GPIO ports
• One shared SPI/I2C interface
• One I2S port
Debugging
• ARM9 JTAG debug interface
• JTAG Boundary Scan Support
Power Management
• CPU and system clock speed step-down options
• Ethernet port Wake-on-LAN
• DDR and PCI power down
Operating Voltage
• 1.3V power for core
• 3.3V power for I/O
• 2.5V or 2.6V power for DDR memory interface
Reference Hardware and Software Evaluation Kit
• Hardware evaluation Kit
• Software Evaluation Kit includes WinCE BSP, Open
WRT BSP, Linux based SOHO Router packages
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2011
M9999-051111-4.0
1 page  
Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
Contents
System Level Applications ...................................................................................................................................................... 9
Pin Description: Signal Descriptions by Group ..................................................................................................................... 10
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 11
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 12
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 13
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 14
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 15
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 16
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 17
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 18
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 19
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 20
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 21
Pin Description: Signal Descriptions by Group (Continued) ................................................................................................. 22
Pin Description: Power-up Strapping Options....................................................................................................................... 23
Pin Description: Power-up Strapping Options (Continued)................................................................................................... 24
Pin Description: Power-up Strapping Options (Continued)................................................................................................... 25
Pin Description: Power-up Strapping Options (Continued)................................................................................................... 26
Functional Description........................................................................................................................................................... 27
ARM High-Performance Processor...................................................................................................................................................... 28
FLASH/ROM/SRAM Memory and External I/O Interface..................................................................................................................... 28
NAND Flash Memory Interface............................................................................................................................................................ 30
DDR Controller .................................................................................................................................................................................... 31
SDIO/SD Host Controller ..................................................................................................................................................................... 35
IP Security Engine ............................................................................................................................................................................... 35
USB 2.0 Interface ................................................................................................................................................................................ 36
PCI Interface........................................................................................................................................................................................ 37
Ethernet MAC Ports (Port 0 = WAN, Port 1 = LAN) ............................................................................................................................. 37
Wake-on-LAN ............................................................................................................................................................... 37
Link Change.................................................................................................................................................................. 38
Wake-up Packet ........................................................................................................................................................... 38
Magic Packet ................................................................................................................................................................ 38
IPv6 Support ................................................................................................................................................................. 39
DMA Controller .................................................................................................................................................................................... 39
UART Interface.................................................................................................................................................................................... 39
Timers and Watchdog.......................................................................................................................................................................... 39
GPIO.................................................................................................................................................................................................... 39
May 2011
5 M9999-051111-4.0
5 Page 
Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
Pin Description: Signal Descriptions by Group (Continued)
Pin Number
T2, U1, L5,
N4, P3, R2,
T1, M4, K5,
N3, P2, R1,
L4, M3, P1,
K4
L3
Pin Name
SDATA[15..0]
ECS2
Pin Type
Ipu/O
O
Pin Description
SRAM DATA Bus.
Bidirectional Bus for 16-bit DATA In and DATA Out. The KSZ9692PB,
KSZ9692PB-S also supports 8-bit data bus for ROM/SRAM/FLASH/EXTIO
cycles.
This data bus is shared between NAND, ROM/SRAM/FLASH/EXTIO devices.
External I/O Chip Select 2, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate which
of the three I/O banks is selected.
N1 ECS1 O External I/O Chip Select 1, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate which
of the three I/O banks is selected.
M2 ECS0 O External I/O Chip Select 0, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate which
of the three I/O banks is selected.
K3
RCSN1
O ROM/SRAM/FLASH(NOR) Chip select 1, asserted Low.
The KSZ9692PB, KSZ9692PB-S can access up to two external
ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to map
the CPU addresses into physical memory banks.
L1
RCSN0
O ROM/SRAM/FLASH(NOR) Chip select 0, asserted Low.
The KSZ9692PB, KSZ9692PB-S can access up to two external
ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to map
the CPU addresses into physical memory banks.
This bank is configurable as boot option
N2 EWAITN I External Wait asserted Low.
This signal is asserted when an external I/O device or
ROM/SRAM/FLASH(NOR) bank needs more access cycles than those defined
in the corresponding control register.
M1
EROEN
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
(WRSTPLS)
When asserted, this signal controls the output enable port of the specified
ROM/SRAM/FLASH memory and EXTIO device.
J5
ERWEN1
O ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, this signal controls the byte write enable of the memory device
SDATA[15..8] for ROM/SRAM/FLASH and EXTIO access.
J4
ERWEN0
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, this signal controls the byte write enable of the memory device
SDATA[7..0 or 15..0] for ROM/SRAM/FLASH and EXTIO access.
May 2011
11 M9999-051111-4.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ9692PB.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KSZ9692PB | Integrated Gigabit Networking and Communications Controller | Micrel Semiconductor |
| KSZ9692PB-S | Integrated Gigabit Networking and Communications Controller | Micrel Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |