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PDF KSZ9692XPB Data sheet ( Hoja de datos )
| Número de pieza | KSZ9692XPB | |
| Descripción | Integrated Gigabit Networking and Communications Controller | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KSZ9692MPB/KSZ9692XPB
Integrated Gigabit Networking and
Communications Controller
Rev. 4.0
General Description
The KSZ9692MPB/KSZ9692XPB is a highly-integrated
System-on-Chip (SoC) containing an ARM 922T 32-bit
processor and a rich set of peripherals to address the cost-
sensitive, high-performance needs of a wide variety of
high-bandwidth networking and communications
applications.
Features
ARM 922T High-Performance Processor Core
• 250 MHz ARM 922T RISC processor core
• 8KB I-cache and 8KB D-cache
• Configurable Memory Management Unit (MMU) for
Linux and WinCE
Memory Controller
• 8/16-bit external bus interface for FLASH, ROM, SRAM,
and external I/O
• NAND FLASH controller with boot option
• 200MHz 32-bit DDR controller
• Two JEDEC Specification JESD82-1-compliant
differential clock drivers for a glueless DDR interface
solution
Ethernet Interfaces
• Two Gb (10/100/1000 Mbps) MACs
• MII or RGMII interface
• Fully compliant with IEEE 802.3 Ethernet standards
PCI Interface
• Version PCI 2.3
• 32-bit 33/66 MHz
• Integrated PCI Arbiter supports three external masters
for KSZ9692MPB and one external master for
KSZ9692XPB
• Configurable as Host bridge or Guest device
• Glueless Support for mini-PCI or CardBus devices
Dual High-Speed USB 2.0 Interfaces
• Two USB2.0 ports with integrated PHY
• Can be configured as 2-port host, or host + device
SDIO/SD Host Controller (for KSZ9692MPB only)
• Meets SD Host Controller Standard Specification
Version 1.0
• Meets SDIO card specification Version 1.0
DMA Controllers
• Dedicated DMA channels for PCI, USB, SDIO and
Ethernet ports.
Peripherals
• Four high-speed UART ports up to 5 Mbps
• Two programmable 32-bit timers with watchdog timer
capability
• Interrupt Controller
• Twenty GPIO ports
• One shared SPI/I2C interface
• One I2S port
Debugging
• ARM9 JTAG debug interface
• JTAG Boundary Scan Support
Power Management
• CPU and system clock speed step-down options
• Ethernet port Wake-on-LAN
• DDR and PCI power down
Operating Voltage
• 1.3V power for core
• 3.3V power for I/O
• 2.5V or 2.6V power for DDR memory interface
Reference Hardware and Software Evaluation Kit
• Hardware Evaluation Kit
• Software Evaluation Kit includes WinCE BSP, Open
WRT BSP, Linux based SOHO Router packages
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2010
M9999-031810-4.0
1 page  
Micrel, Inc.
KSZ9692MPB/KSZ9692XPB
List of Figures
Note: SDIO block for KSZ9692MPB only................................................................................................................................ 2
Figure 1. KSZ9692MPB/XPB Block Diagram ........................................................................................................................ 2
Figure 2. Peripheral Options and Examples ........................................................................................................................... 6
Figure 3. KSZ9692MPB Functional Block Diagram ............................................................................................................... 8
Figure 4. KSZ9692XPB Functional Block Diagram................................................................................................................ 9
Figure 4. Static Memory Interface Examples ........................................................................................................................ 11
Figure 5. External I/O Interface Examples ............................................................................................................................ 11
Figure 7. 16-bit NAND Interface Examples........................................................................................................................... 13
Figure 8. Single 16-bit DDR Memory Device Interface Example.......................................................................................... 14
Figure 10. Burst DDR Read Timing ...................................................................................................................................... 16
Figure 11. Burst DDR Write Timing....................................................................................................................................... 16
Figure 12. USB 2.0 Configuration as Two-Port Host ............................................................................................................ 18
Figure 13. USB 2.0 Configuration as Host + Device............................................................................................................. 18
Figure 14. Reset Circuit ........................................................................................................................................................ 23
Figure 15. Power and Clocks ................................................................................................................................................ 23
Figure 16. Reset Timing........................................................................................................................................................ 40
Figure 17. Static Memory Read Cycle .................................................................................................................................. 40
Figure 18. Static Memory Write Cycle .................................................................................................................................. 41
Figure 19. External I/O Read and Write Cycles .................................................................................................................... 41
Figure 20. Ball Grid Array Map.............................................................................................................................................. 43
Figure 21. 400-Pin PBGA...................................................................................................................................................... 44
List of Tables
Table 1. Reset Timing Parameters ....................................................................................................................................... 40
Table 2. Programmable Static Memory Timing Parameters................................................................................................. 41
Table 3. External I/O Memory Timing Parameters................................................................................................................ 42
Table 4. Programmable External I/O Timing Parameters..................................................................................................... 42
March 2010
5 M9999-031810-4.0
5 Page 
Micrel, Inc.
KSZ9692MPB/KSZ9692XPB
Figure 4. Static Memory Interface Examples
March 2010
Figure 5. External I/O Interface Examples
11
M9999-031810-4.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ9692XPB.PDF ] | |
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