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PDF KSZ8893MBL Data sheet ( Hoja de datos )

Número de pieza KSZ8893MBL
Descripción Integrated 3-Port 10/100 Managed Switch
Fabricantes Micrel Semiconductor　
Logotipo Micrel Semiconductor Logotipo



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No Preview Available ! KSZ8893MBL Hoja de datos, Descripción, Manual

KSZ8893MQL/MBL
Integrated 3-Port 10/100 Managed
Switch with PHYs
Rev. 1.6
General Description
The KSZ8893MQL/MBL, a highly integrated layer 2
managed switch, is designed for low port count,
cost-sensitive 10/100 Mbps switch systems. It offers
an extensive feature set that includes rate limiting,
tag/port-based VLAN, QoS priority, management,
management information base (MIB) counters,
RMII/MII/SNI, and CPU control/data interfaces to
effectively address both current and emerging Fast
Ethernet applications.
The KSZ8893MQL/MBL contains two 10/100
transceivers
with patented mixed-signal low-power technology,
three media access control (MAC) units, a high-
speed non-blocking switch fabric, a dedicated
address lookup engine, and an on-chip frame buffer
memory.
Both PHY units support 10BASE-T and 100BASE-
TX. In addition, one PHY unit supports 100BASE-FX.
The KSZ8893MQL/MBL comes in a lead-free
package, and is also available in industrial
temperature-grade KS8893MQLI/MBLI and
Automotive-grade KSZ8893 MQL AM. (See Ordering
Information).
___________________________________________________________________________________________________
Functional Diagram
HP AUTO
MDIX
HP AUTO
MDIX
RMII/MII/
SNI
10/100
T/TX/FX
PHY 1
10/100
T/TX
PHY 2
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
SNI
1K LOOK-UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFERS
SPI
SPI
MIB
COUNTERS
MIIM
SMI
I2C
P1 LED[3:0]
P2 LED[3:0]
LED
DRIVERS
CONTROL
REGISTERS
EEPROM
INTERFACE
STRAP IN
CONFIGURATION
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
February 2010
1 M9999-021110-1.6

1 page




KSZ8893MBL pdf
Micrel, Inc.
KSZ8893MQL/MBL
QoS Priority Support...........................................................................................................................................................48
Port-Based Priority..............................................................................................................................................................48
802.1p-Based Priority..........................................................................................................................................................48
DiffServ-Based Priority .......................................................................................................................................................49
Rate Limiting Support .........................................................................................................................................................49
Unicast MAC Address Filtering..........................................................................................................................................49
Configuration Interface .......................................................................................................................................................50
I2C Master Serial Bus Configuration ..............................................................................................................................50
I2C Slave Serial Bus Configuration ................................................................................................................................51
SPI Slave Serial Bus Configuration ...............................................................................................................................51
Loopback Support...............................................................................................................................................................54
Far-end Loopback..........................................................................................................................................................54
Near-end (Remote) Loopback .......................................................................................................................................55
MII Management (MIIM) Registers..................................................................................................... 56
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control.........................................................................57
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control.........................................................................57
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status...........................................................................58
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status...........................................................................58
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High ..................................................................................58
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High ..................................................................................58
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low ...................................................................................58
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low ...................................................................................58
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................59
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability ...................................59
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................59
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability .......................................59
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status...........................................................60
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status...........................................................60
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status ...................................................60
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status ...................................................60
Register Map: Switch & PHY (8-bit registers) .................................................................................. 61
Global Registers ............................................................................................................................................................61
Port Registers ................................................................................................................................................................61
Advanced Control Registers ..........................................................................................................................................61
Global Registers..................................................................................................................................................................61
Register 0 (0x00): Chip ID0 ...........................................................................................................................................61
Register 1 (0x01): Chip ID1 / Start Switch .....................................................................................................................62
Register 2 (0x02): Global Control 0 ...............................................................................................................................62
Register 3 (0x03): Global Control 1 ...............................................................................................................................63
Register 4 (0x04): Global Control 2 ...............................................................................................................................63
Register 4 (0x04): Global Control 2 (continued).............................................................................................................64
Register 5 (0x05): Global Control 3 ...............................................................................................................................64
Register 5 (0x05): Global Control 3 (continued).............................................................................................................65
Register 6 (0x06): Global Control 4 ...............................................................................................................................65
Register 6 (0x06): Global Control 4 (continued).............................................................................................................66
Register 7 (0x07): Global Control 5 ...............................................................................................................................66
Register 8 (0x08): Global Control 6 ...............................................................................................................................66
Register 9 (0x09): Global Control 7 ...............................................................................................................................66
Register 10 (0x0A): Global Control 8 .............................................................................................................................66
Register 11 (0x0B): Global Control 9 .............................................................................................................................67
Register 12 (0x0C): Global Control 10...........................................................................................................................67
Register 13 (0x0D): Global Control 11...........................................................................................................................68
Register 14 (0x0E): Global Control 12 ...........................................................................................................................68
Register 15 (0x0F): Global Control 13 ...........................................................................................................................68
Port Registers......................................................................................................................................................................68
Register 16 (0x10): Port 1 Control 0 ..............................................................................................................................69
Register 32 (0x20): Port 2 Control 0 ..............................................................................................................................69
Register 48 (0x30): Port 3 Control 0 ..............................................................................................................................69
Register 17 (0x11): Port 1 Control 1 ..............................................................................................................................70
Register 33 (0x21): Port 2 Control 1 ..............................................................................................................................70
Register 49 (0x31): Port 3 Control 1 ..............................................................................................................................70
February 2010
5 M9999-021110-1.6

5 Page





KSZ8893MBL arduino
Micrel, Inc.
KSZ8893MQL/MBL
Pin Number
4
5
6
Pin Name
P2LED2
P2LED1
P2LED0
Type (1)
Ipu/O
Ipu/O
Ipu/O
Description
Port 2 LED Indicators
(apply to all modes of operation, except Repeater Mode)
P2LED3
P2LED2
P2LED1
P2LED0
[LEDSEL1, LEDSEL0]
[0, 0]
[0, 1]
——
Link/Act
100Link/Act
Full duplex/Col 10Link/Act
Speed
Full duplex
P2LED3
P2LED2
P2LED1
P2LED0
[LEDSEL1, LEDSEL0]
[1, 0]
[1, 1]
Act —
Link —
Full duplex/Col —
Speed
—
Link/Act, 100Link/Act, 10Link/Act : Low (link), High (no link),
Toggle (transmit / receive activity)
Full duplex/Col : Low (full duplex), High (half duplex), Toggles
(collision)
Speed : Low (100BASE-TX), High (10BASE-T)
Full duplex : Low (full duplex), High (half duplex)
Act : Toggle (transmit / receive activity)
Link : Low (link), High (no link)
Repeater Mode (only)
[LEDSEL1, LEDSEL0]
[0, 0]
P2LED3
RPT_ACT
P2LED2
RPT_ERR3
P2LED1
RPT_ERR2
P2LED0
RPT_ERR1
RPT_ACT : Low (activity)
RPT_ERR# (# = port) : Low (error status due to either
isolation, partition, jabber, or JK error)
Notes:
LEDSEL0 is external strap-in pin 70.
LEDSEL1 is external strap-in pin 23.
P2LED3 is pin 20.
During reset, P2LED[2:0] are inputs for internal testing.
7 DGND Gnd Digital ground
8
VDDIO
P
3.3V digital VDD
Note:
1. P = Power supply.
Gnd = Ground.
Ipu/O = Input with internal pull-up during reset, output pin otherwise.
February 2010
11 M9999-021110-1.6

11 Page







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