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AT24C01C 데이터시트 PDF




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부품번호 AT24C01C 기능
기능 EEPROM
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AT24C01C 데이터시트, 핀배열, 회로
AT24C01C and AT24C02C
I2C-Compatible (2-wire) Serial EEPROM
1-Kbit (128 x 8), 2-Kbit (256 x 8)
DATASHEET
Features
Low-voltage Operation
̶ VCC = 1.7V to 5.5V
Internally Organized as 128 x 8 (1K) or 256 x 8 (2K)
I2C Compatible (2-wire) Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page Write Mode
̶ Partial Page Writes Allowed
Self-timed Write Cycle (5ms max)
High-reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Green Package Options (Pb/Halide-free/RoHS-compliant)
̶ 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 5-lead
SOT23, and 8-ball VFBGA
Die Sale Options: Wafer Form and Tape and Reel Available
Description
The Atmel® AT24C01C/02C provides 1024/2048-bits of Serial Electrically
Erasable and Programmable Read-Only Memory (EEPROM) organized as
128/256 words of eight bits each. Both devices include a cascading feature that
allows up to eight devices to share a common 2-wire bus. These devices are
optimized for use in many industrial and commercial applications where low
power and low voltage operation are essential. The AT24C01C/02C are available
in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN,
5-lead SOT23, and 8-ball VFBGA packages. In addition, the entire family
operates from 1.7V to 5.5V VCC.
Atmel-8700H-SEEPROM-AT24C01C-02C-Datasheet_122016




AT24C01C pdf, 반도체, 판매, 대치품
4. Memory Organization
AT24C01C, 1K Serial EEPROM: Internally organized with 16 pages of eight bytes each, the 1K requires a 7-bit
data word address for random word addressing.
AT24C02C, 2K Serial EEPROM: Internally organized with 32 pages of eight bytes each, the 2K requires an
8-bit data word address for random word addressing.
4.1 Pin Capacitance
Table 4-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 1.7V to 5.5V.
Symbol Test Condition
Max Units
CI/O Input/Output Capacitance (SDA)
CIN Input Capacitance (A0, A1, A2, SCL)
8 pF
6 pF
Note: 1. This parameter is characterized and is not 100% tested.
Conditions
VI/O = 0V
VIN = 0V
4.2 DC Characteristics
Table 4-2. DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted).
Symbol Parameter
Test Condition
Min
Typ
Max Units
VCC1
VCC2
VCC3
ICC1
ICC2
ISB1
ISB2
ISB3
ILI
ILO
VIL
VIH
VOL1
VOL2
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.7V
Standby Current VCC = 2.5V
Standby Current VCC = 5.5V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
Input High Level(1)
Output Low Level VCC = 1.7V
Output Low Level VCC = 3.0V
Read at 400kHz
Write at 400kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
IOL = 0.15mA
IOL = 2.1mA
1.7
2.5
4.5
-0.6
VCC x 0.7
5.5
5.5
5.5
0.4 1.0
2.0 3.0
1.0
2.0
6.0
0.10 3.0
0.05 3.0
VCC x 0.3
VCC + 0.5
0.2
0.4
V
V
V
mA
mA
μA
μA
μA
μA
μA
V
V
V
V
Note: 1. VIL min and VIH max are reference only and are not tested.
4 AT24C01C/02C [DATASHEET]
Atmel-8700H-SEEPROM-AT24C01C-02C-Datasheet_122016

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AT24C01C 전자부품, 판매, 대치품
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
Figure 6-3. Output Acknowledge
SCL
1
89
Data In
Data Out
Start
Acknowledge
Standby Mode: The AT24C01C/02C features a low-power standby mode which is enabled:
Upon power-up.
After the receipt of the Stop condition and the completion of any internal operations.
2-wire Software Reset: After an interruption in protocol, power-loss, or system reset, any 2-wire part can be
reset by following these steps:
1. Create a Start condition (if possible).
2. Clock nine cycles.
3. Create another Start condition followed by Stop condition as shown in Figure 6-4.
The device will be ready for the next communication after above steps have been completed. The device should
be ready for the next communication after above steps have been completed. In the event that the device is still
non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device.
Figure 6-4. Software Reset
Dummy Clock Cycles
SCL 1 2 3
Start
Condition
SDA
89
Start
Condition
Stop
Condition
AT24C01C/02C [DATASHEET]
Atmel-8700H-SEEPROM-AT24C01C-02C-Datasheet_122016
7

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