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부품번호 ZSSC1856 기능
기능 Intelligent Battery Sensor IC
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ZSSC1856 데이터시트, 핀배열, 회로
Data Sheet
Rev. 1.00 / April 2012
ZSSC1856
Intelligent Battery Sensor IC




ZSSC1856 pdf, 반도체, 판매, 대치품
ZSSC1856
Intelligent Battery Sensor IC
Contents
1 IC CHARACTERISTICS ....................................................................................................................................12
1.1 Absolute Maximum Ratings ........................................................................................................................12
1.2 Recommended Operating Conditions ........................................................................................................12
1.3 Electrical Parameters..................................................................................................................................13
1.4 Current Consumption..................................................................................................................................19
1.5 Output Pads Drive Strength........................................................................................................................19
2 CIRCUIT DESCRIPTION ..................................................................................................................................20
2.1 Overview .....................................................................................................................................................20
2.2 Digital Block Diagram SBC .........................................................................................................................22
2.3 Block Diagram MCU ...................................................................................................................................23
2.4 System Power States .................................................................................................................................24
2.4.1 MCU-ON Power State .........................................................................................................................24
2.4.2 MCU-SLP Power State........................................................................................................................25
2.4.3 MCU-DEEP Power State.....................................................................................................................25
2.4.4 LP Power State....................................................................................................................................25
2.4.5 ULP Power State .................................................................................................................................26
2.4.6 OFF Power State .................................................................................................................................26
3 Functional Block Descriptions SBC ...................................................................................................................28
3.1 SPI Communication between the MCU and SBC ......................................................................................28
3.1.1 SPI Protocol.........................................................................................................................................28
3.2 SBC Register Map ......................................................................................................................................30
3.3 SBC Clock and Reset Logic .......................................................................................................................33
3.3.1 Clocks ..................................................................................................................................................33
3.3.2 Trimming the Low-Power Oscillator.....................................................................................................34
3.3.3 Resets..................................................................................................................................................36
3.4 SBC Watchdog Timer .................................................................................................................................38
3.5 SBC Sleep Timer ........................................................................................................................................41
3.6 SBC Interrupt Controller .............................................................................................................................44
3.7 SBC Power Management Unit (PMU) ........................................................................................................46
3.7.1 FP State...............................................................................................................................................47
3.7.2 LP and ULP States ..............................................................................................................................48
3.7.3 OFF State ............................................................................................................................................55
3.8 SBC ADC Unit ............................................................................................................................................57
3.8.1 ADC Clocks .........................................................................................................................................58
3.8.2 ADC Data Path ....................................................................................................................................62
3.8.3 ADC Operating Modes and Result Registers......................................................................................66
3.8.4 ADC Control and Conversion Timing ..................................................................................................76
3.8.5 Diagnostic Features.............................................................................................................................84
3.8.6 Digital Features ...................................................................................................................................86
3.9 SBC LIN Support Logic...............................................................................................................................87
3.9.1 TXD Timeout Detection .......................................................................................................................88
3.9.2 LIN Short Detection .............................................................................................................................88
3.9.3 LIN Testing ..........................................................................................................................................89
3.10 SBC OTP ....................................................................................................................................................91
3.11 Miscellaneous Registers.............................................................................................................................92
Data Sheet
April 24, 2012
© 2012 Zentrum Mikroelektronik Dresden AG Rev.1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
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ZSSC1856 전자부품, 판매, 대치품
ZSSC1856
Intelligent Battery Sensor IC
List of Figures
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 3.1
Figure 3.2
Figure 3.3
IBS Stacked Die Assembly ..................................................................................................................20
Functional Block Diagram ....................................................................................................................21
Block Diagram of the Digital Section of the SBC .................................................................................22
System Power States...........................................................................................................................24
Read and Write Burst Access to the SBC ...........................................................................................29
Structure of the Watchdog Timer .........................................................................................................38
Structure of the Sleep Timer ................................................................................................................42
Figure 3.4 Generation of Interrupt and Wake-up ..................................................................................................44
Figure 3.5 LP/ULP State without any Measurements ...........................................................................................49
Figure 3.6 LP/ULP State Performing Current Measurements Only ......................................................................50
Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements with discCvtCnt
== 2 ......................................................................................................................................................52
Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements with discCvtCnt
== 5 ......................................................................................................................................................52
Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements with discCvtCnt
== 1 ......................................................................................................................................................52
Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements ..................................................53
Figure 3.11 LP/ULP State Performing Continuous Current and Voltage Measurements .......................................54
Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem ...................................................57
Figure 3.13 FP ADC Clocking Scheme for sdmPos = sdmPos2 = 2; sdmClkDivFp = 1; sdmChopClkDiv = 0 .59
Figure 3.14 FP ADC Clocking for sdmPos = 1 and sdmPos2 = 4; sdmClkDivFp = 1; sdmChopClkDiv = 0......59
Figure 3.15 FP ADC Clocking for sdmPos = 3 and sdmPos2 = 0; sdmClkDivFp = 1; sdmChopClkDiv = 0......60
Figure 3.16 FP ADC Clocking for sdmPos = 0 and sdmPos2 = 3; sdmClkDivFp = 1; sdmChopClkDiv = 0......60
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivFp = 5; sdmChopClkDiv = 0 ......................................61
Figure 3.18 Functional Block Diagram of the Digital ADC Data Path .....................................................................62
Figure 3.19 Data Post Correction............................................................................................................................63
Figure 3.20 Data Representation through Data Post Correction including Over-range and Overflow Levels........64
Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current .................64
Figure 3.22 Individual SRCS...................................................................................................................................77
Figure 3.23 Individual MRCS (Example for Result Counter of 3) ...........................................................................77
Figure 3.24 Continuous SRCS................................................................................................................................78
Figure 3.25 Continuous MRCS (Example for Result Counter of 3) ........................................................................78
Figure 3.26 Stopping Continuous SRCS ................................................................................................................78
Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3) .........................................................79
Figure 3.28 Interrupting a Continuous SRCS .........................................................................................................79
Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3) ..................................................79
Figure 3.30 Signal Behavior of adcMode................................................................................................................80
Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for
Different Configurations of the Average Filter......................................................................................82
Figure 3.32 Timing for External Temperature Measurements without Chopping when No Average Filter is
Enabled ................................................................................................................................................83
Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping....................84
Figure 3.34 Timing for External Temperature Measurements using Chopping ......................................................84
Figure 3.35 Usage of Register adcCaccTh for the Digital ADC BIST....................................................................86
Figure 3.36 Bit Stream of ADC Interface Test at STO Pad.....................................................................................87
Data Sheet
April 24, 2012
© 2012 Zentrum Mikroelektronik Dresden AG Rev.1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
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부품번호상세설명 및 기능제조사
ZSSC1856

Intelligent Battery Sensor IC

Zentrum Mikroelektronik Dresden
Zentrum Mikroelektronik Dresden

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