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SH6613D 데이터시트 PDF




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부품번호 SH6613D 기능
기능 4K 4-Bit Microcontroller
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SH6613D 데이터시트, 핀배열, 회로
SH6613D
4K 4-Bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 4096×16 bits
RAM: 512×4 bits
Operation voltage: 2.4V – 6.0V
8 CMOS bi-directional I/O pins
4-Level subroutine nesting (include interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power-on reset
Powerful interrupt sources:
- External interrupts ( INT0 ).
- Internal interrupt (Timer0).
- Internal interrupt (Base Timer).
- Port's falling edge interrupt: PORTB ( INT1 )
8-bit Base timer
LCD driver: 136 dots(1/4 duty 1/3 bias)
LCD used as scan output
Built-in dual tone PSG with one noise generator
2 Clock source
OSC: (code option select crystal or RC type)
- Crystal oscillator 32.768K
- RC oscillator: 262K
OSCX: (system register select ceramic or RC type)
- Ceramic oscillator 455K
- RC oscillator 1.8M or 2M
Instruction cycle time:
- 122.07µs for 32.768 kHz crystal
- 15.27µs for 262 kHz RC
- 8.79µs for 455KHz ceramic
- 2.22µs for 1.8 MHz RC
- 2µs for 2.0 MHz RC
Two low power operation mode: HALT and STOP
Low power consumption
General Description
SH6613D is a single chip microcontroller integrated with SRAM, timer and dual-tone PSG, LCD driver and I/O port. This chip
builds in a dual-oscillator to enhance the total chip performance.
Pad Diagram
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SSSSSSSSSSSS
EEEEEEEEEEEE
GGGGGGGGGGGG
112222222222
890123456789
SSS
EEE
GGG
333
012
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
45 28
46 27
47 26
48 25
49 24
50 23
51
SH6613D
22
52 21
53 GND 20
54 19
55 18
56 17
VDD
57 9 16
58 1 2 3 4 5 6 7 8
10 11 12 13 14 15
_
S S S V V V VT RPP P P P P
E E E L 1 2 3 E E C. B. B. B. B. A.
GGGC
321D
S S1 3 21 03
T
E
T
SEG33
SEG34
COM4
COM3
COM2
COM1
OSCI
OSCO
PC.0
OSCXO
OSCXI
PA.0
PA.1
PA.2
1/33 V1.0




SH6613D pdf, 반도체, 판매, 대치품
SH6613D
3. RAM
Built-in SRAM contains general-purpose data memory, LCD RAM, and system registers. They can be accessed by direct
addressing in one instruction.
The following is the memory allocation map:
$000~$01F: System register and I/O;
$020~$1FF: Data memory (480×4bits,partitioned into 4 banks).
$300~$321, $350~$36D: LCD RAM space (34×4 bits).
The configuration of system register
Address
$00
$01
$02
$03
$04
$05
$06~$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
Bit3
IEX
IRQX
TM0.3
BTM.3
T0L.3
T0H.3
-
PA.3
PB.3
-
PACR.3
PBCR.3
-
TBR.3
INX.3
DPL3
-
-
PPULL
OXS
LPS1
LPD
C1.3
OCT1
C2.3
C2.7
C2.11
OCT2
VOL1
SEL1
-
Bit2
IET0
IRQT0
TM0.2
BTM.2
T0L.2
T0H.2
-
PA.2
PB.2
-
PACR.2
PBCR.2
-
TBR.2
INX.2
DPL2
DPM.2
DPH.2
PAM2
-
LPS0
O/S
C1.2
C1.6
C2.2
C2.6
C2.10
C2.14
VOL0
SEL0
-
Bit1
IEBT
IRQBT
TM0.1
BTM.1
T0L.1
T0H.1
-
PA.1
PB.1
PC.1
PACR.1
PBCR.1
-
TBR.1
INX1
DPL1
DPM.1
DPH.1
PAM1
OXM
LCDOFF
-
C1.1
C1.5
C2.1
C2.5
C2.9
C2.13
CH2EN
C2M
-
Bit0
IEP
IRQP
TM0.0
BTM.0
T0L.0
T0H.0
-
PA.0
PB.0
PC.0
PACR.0
PBCR.0
-
TBR.0
INX.0
DPL0
DPM.0
DPH.0
HLM
OXON
Should
be
set ”1”
-
C1.0
C1.4
C2.0
C2.4
C2.8
C2.12
CH1EN
C1M
-
Function
Initial
Value
Interrupt enable flags
0000
Interrupt request flags
0000
Timer0 mode register
0000
Base timer mode register
0000
Timer0 load/counter low nibble
0000
Timer0 load/counter high nibble
0000
Reserved
-
PORTA
0000
PORTB
0000
Bonding option
01(default)
Set PORTA to be output port
0000
Set PORTB to be output port
0000
Reserved
-
Table branch register
0000
Index register(INX)
0000
Data pointer for INX low nibble
0000
Data pointer for INX middle nibble
0000
Data pointer for INX high nibble
0000
Bit1,2:PA.1 & PA.2 as PSG output or I/O PORT 0000
Bit0:Heavy load mode
Bit3:Port pull-up control
Bit0:Turn on OSCX oscillator
0000
Bit1:CPU clocks select (1:OSCX/0:OSC)
Bit3:OSCX type selection
Bit0:Programmer should be set “1”
0000
Bit1:LCD off
Bit2,3:LCD frequency control
Bit2:Set LCD segment as output
0000
Bit3:LCD Power degrade
PSG channel 1 low nibble
0000
PSG channel 1high nibble
0000
Bit3:channel 1 octave shift control
PSG channel 2 nibble 1 or alarm output
0000
PSG channel 2 nibble 2
0000
PSG channel 2 nibble 3
0000
PSG channel 2 nibble 4
0000
Bit3:channel 2 octave shift control
Bit0,Bit1:Channel 1,2 enable
0000
Bit2,Bit3:volume control
Bit0,1:PSG1,PSG2 mode control
0000
Bit2,3:PSG1,PSG2 clock source selection
Reserved
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R
W
W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
-
*System Register $00~$12 refer to "SH6610C User manual".
4/33 V1.0

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SH6613D 전자부품, 판매, 대치품
SH6613D
5.4 Control of oscillator
The oscillator control register configuration is shown as blow.
Add.
Bit3 Bit2
$14
OXS
-
OXON: OSCX oscillation on/off.
0:Turn off OSCX oscillation
OXM: switching system clock.
0:select OSC as system clock
OXS: OSCX oscillator type selection
0:OSCX set as ceramic oscillator
Bit1
OXM
Bit0
OXON
1:Turn on OSCX oscillation
1:select OSCX as system clock
1:OSCX set as RC oscillator
5.5 Programming notes
It takes at least 5 ms for the OSCX oscillation circuit to go on until the oscillation stabilizes. When switching the CPU system
clock from OSC to OSCX, you must wait a minimum of 5ms since the OSCX oscillation goes. However, the start time varies a lot
with respect to oscillator characteristics and the condition of use. So the waiting time depends on applications. When switching
from OSCX to OSC, and turn off OSCX in one instruction. The OSCX turn off control would be delayed for one instruction cycle
automatically to prevent CPU operation error.
6. System clock
The system clock is varies as the clock source changes. The following table shows the instruction execution time according to
each frequency of the system clock source.
32.768 Xtal(OSC ) 262K RC(OSC ) 455K ceramic Xtal(OSCX) 1.8M RC(OSCX) 2M RC(OSCX)
Cycle time 122.07 µs
17.778 µs
8.79 µs
2.22 µs
2µs
7. I/O PORTs
The MCU provides 8-bidirectional I/O pins. Each I/O pin contains pull-up MOS controllable by program. When every I/O is used
as input, the PORT control register (PACR, PBCR) controls ON/OFF of the output buffer.
7.1 PORTA~B
These ports contain 8-bidirectional I/O ports.
The circuit configuration of PORTA~B as below.
PULLUP
PULL_UP
PMOS
PORT
CONTROL
REGISTER
PORTX
PORT
DATA
REGISTER
DATAINPUT
RD_INPUT
I/O ports of SH6613D can be accessed by read/write system register.
User can output any value to any I/O port bit at any time.
Memory map addresses are listed as follow:
Address
$08
$09
Bit3
PORTA.3
PORTB.3
Bit2
PORTA.2
PORTB.2
Bit1
PORTA.1
PORTB.1
Bit0
PORTA.0
PORTB.0
7/33 V1.0

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