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PDF SH66K12 Data sheet ( Hoja de datos )
| Número de pieza | SH66K12 | |
| Descripción | Mask 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH66K12
MASK 4-bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit microcontroller with
LCD driver
ROM: 2048 X 16 bits
RAM: 256 X 4 bits (Data memory)
Operation voltage: 2.5V - 5.4V
16 CMOS I/O pins
- CMOS or Open Drain (code option)
4 level subroutine nesting (including interrupts)
Two 8-bit timer/counter with pre-divider circuit
Oscillator warm-up timer
4 priority interrupt sources:
- External interrupt (falling edge)
- Timer0 interrupt
- Timer1 interrupt
- PortB interrupt (falling edge)
Oscillator
- 32.768KHz crystal or 262K RC (code option)
Instruction cycle time:
- 4/32.768KHz (≈ 122µs) for 32.768KHz OSC clock
- 4/262KHz (≈ 15µs) for 262KHz OSC clock
LCD driver:
- 4 X 26 (1/4 duty, 1/3 bias or 1/3 duty, 1/2 bias)
Two low power operation modes: HALT or STOP mode
Built-in alarm generator carrier frequency:
- 2KHz or 4KHz (code option)
Low power consumption (Iop < 10µA, 32.768KHz, 3V)
Bonding option for multi-code software
Available in CHIP FORM
General Description
SH66K12 is a single-chip microcontroller integrated with an SH6610C 4-bit CPU core, SRAM, timer, alarm generator, LCD
driver, I/O port, and program ROM.
Pad Configuration
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SSSSSSSSSS
EEEEEEEEEECC
GGGGGGGGGGOO
1 1 1 2 2 2 2 2 2 2 MM
789012345612
38 37 36 35 34 33 32 31 30 29 28 27
39 26
40 25
41 24
42 23
43 22 B1
44 21
45 SH66K12 20
46 19
47 18
48 17
49 16
50 15
51 5
14
52 1 2 3 4 B0 6 7 8 9 10 11 12 13
COM3
COM4
OSCI
OSCO
GND
PORTD3
PORTD2
PORTD1
PORTD0
PORTC3
PORTC2
PORTC1
PORTC0
PORTB3
S
E
G
2
S
E
G
1
T
E
S
T
R
E
S
E
V
D
D
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
T AAAABBB
0123012
1 V1.0
1 page  
SH66K12
System Register $0D:
Address Bit 3 Bit 2 Bit 1 Bit 0 R/W
Remarks
$0D -
-
B1
B0
R
Bit0: Bonding option 0, internal weak drive
Bit1: Bonding option 1, internal weak drive
XX1 0
XX0 0
B1 bond to GND
XX1 1
B0 bond to VDD
XX0 1
B1 bond to GND and B0 bond to VDD
Power-on
Pull low
Pull high
Yes
GND
B1
VDD
B0
GND
B1
VDD
B0
B1 = 1 B0 = 0
GND
B1
VDD
B0
PCB
B1 = 1 B0 = 1
GND
B1
VDD
B0
PCB
B1 = 0 B0 = 0
B1 = 0 B0 = 1
SH66K12 Bonding Option
Up to 4 different bonding options is possible for the user's needs. The chip's program has 4 different program flows that will vary
depending on which bonding option is used. The readable contents of B1 and B0 will differ depending on bonding.
5
5 Page 
SH66K12
7. Interrupt
Four interrupt sources are available on SH66K12:
- External interrupt ( INT share with PA.0)
- Timer0 interrupt
- Timer1 interrupt
- Port’s falling edge detection interrupt ( PB )
(a) Interrupt Control Bits and Interrupt Service:
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by program.
Those flags are cleared to 0 at initialization by chip reset.
Address
Bit3
Bit2
Bit1
Bit0
Remarks
$00 IEX
IET0
IET1
IEP
interrupt enable flags
$01 IRQX
IRQT0
IRQT1
IRQP
interrupt request flags
When IEx is set to 1 and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are reset to 0 automatically, so when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources.
(b) Interrupt Servicing Sequence Diagram:
Inst. cycle
1
2
3
4
5
Instruction
Execution
N
Interrupt Generated
Instruction
Execution
I1
Interrupt Accepted
Instruction
Execution
I2
Vector Generated
Stacking
Fetch Vector address
Reset IE.X
Start at vector address
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any INTERRUPT enable flag before returning from the
interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt
request is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two
instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt
service will be terminated.
(c) External Interrupt ( INT )
External interrupt is shared with the bit0 of PORTA. When bit3 of system register 0 (IEX) is set to 1, the external interrupt will be
enabled, and a falling edge signal on PA.0 will generate an external interrupt. (Note: while external interrupt is enabled, writing
a “0” to bit0 of PORTA will generate an external interrupt).
8. System Clock
SH66K12 has one clock source. OSC is 32.768KHz crystal or 262KHz RC determined by code option. The OSC generates the
basic clock pulses that provide the system clock to supply CPU and on-chip peripherals (TIMER0, TIMER1, LCD).
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet SH66K12.PDF ] | |
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