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SH66L10A 데이터시트 PDF




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부품번호 SH66L10A 기능
기능 2K 4-bit Microcontroller
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SH66L10A 데이터시트, 핀배열, 회로
SH66L10A
2K 4-bit Micro-controller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro-controller with
LCD driver
ROM: 2K X 16 bits
RAM: 288 X 4 bits
- 32 System Control Register
- 256 Data memory
- 34 LCD RAM
Operation Voltage: 1.2V - 1.7V
16 CMOS Bi-directional I/O pads (PORTC, PORTD can
switch to LCD segment)
4-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Loaded Timers/Counters
Warm-Up Timer
Powerful Interrupt Sources:
- External interrupt (Low active)
- Timer0 interrupt
- Timer1 interrupt
- PORTB & PORTC interrupt (Low active)
Oscillator (Code Option)
- Crystal Oscillator: 32.768kHz
- RC Oscillator:
131kHz
Instruction Cycle Time (4/fOSC)
LCD Driver:
- 34SEG X 4COM (1/4 Duty, 1/3 Bias)
- 34SEG X 3COM (1/3 Duty, 1/2 Bias)
Two Low Power Operation Modes: HALT And STOP
Built-in Watchdog Timer (Code Option)
Built-in Voltage Doubler And Tripler Charge Pump
Circuit
Built-in Alarm Generator
Low power consumption
Bonding option for multi-code software
Available in CHIP FORM
General Description
SH66L10A is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, SRAM, timer, alarm generator,
LCD driver, I/O port, voltage pump and program ROM. The SH66L10A is suitable for calculator application.
Pad Configuration
SEG25
SEG26
PORTC0/SEG27
PORTC1/SEG28
PORTC2/SEG29
PORTC3/SEG30
PORTD0/SEG31
PORTD1/SEG32
PORTD2/SEG33
PORTD3/SEG34
PORTA0
PORTA1
PORTA2
PORTA3
PORTB0
PORTB1
1 56 55 54 53 52 51 50 49 48 47 46 45 44
2 43
3 42
4 41
5 40
6 39
7
8
SH66L10A
38
37
9 36
10 35
11 34
12 33
13 32
14 31
15
19 22
30
16 17 18 B0 20 21 B1 23 24 25 26 27 28 29
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM4
COM3
COM2
COM1
1 V2.1




SH66L10A pdf, 반도체, 판매, 대치품
SH66L10A
Functional Description
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX, DPH,
DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code Bit7 - Bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM (3-bit)
and DPL (4-bit). The addressing range is 000H-3FFH.
Pseudo index address (INX) is used to read or write Data
memory, then RAM address Bit9 - Bit0 which comes from
DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 4 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC by the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 4 levels. If the number of calls and
interrupt requests exceeds 4, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU entering STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $01F
Data memory $020 - $11F:
LCD RAM space: $300 - $321: (34 X 4 bits)
RAM bank table:
Bank0
B=0
Bank1
B=1
Bank2
B=2
Bank6
B=6
$020 - $07F
$080 - $0FF
$100 - $17F
$300 - $3FF
Where, B: RAM bank bit use in instructions
4

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SH66L10A 전자부품, 판매, 대치품
SH66L10A
4. Initial State
4.1. System Register State:
Address
$00
Bit 3
IEX
Bit 2
IET0
Bit 1
IET1
Bit 0
IEP
Power-on Reset
0000
Pad Reset
0000
WDT Reset
0000
$01 IRQX IRQT0 IRQT1 IRQP
0000
0000
0000
$02 - T0M.2 T0M.1 T0M.0
-000
-000
-000
$03 - T1M.2 T1M.1 T1M.0
-000
-000
-000
$04
T0L.3
T0L.2
T0L.1
T0L.0
0000
0000
0000
$05
T0H.3
T0H.2
T0H.1
T0H.0
0000
0000
0000
$06
T1L.3
T1L.2
T1L.1
T1L.0
0000
0000
0000
$07
T1H.3
T1H.2
T1H.1
T1H.0
0000
0000
0000
$08
PA.3
PA.2
PA.1
PA.0
0000
0000
0000
$09
PB.3
PB.2
PB.1
PB.0
0000
0000
0000
$0A
PC.3
PC.2
PC.1
PC.0
0000
0000
0000
$0B
PD.3
PD.2
PD.1
PD.0
0000
0000
0000
$0C - - - -
----
----
----
$0D -
- B1 B0
--uu
--uu
--uu
$0E TBR.3 TBR.2 TBR.1 TBR.0
xxxx
xxxx
uuuu
$0F
INX.3
INX.2
INX.1
INX.0
xxxx
xxxx
uuuu
$10 DPL.3 DPL.2 DPL.1 DPL.0
xxxx
xxxx
uuuu
$11 - DPM.2 DPM.1 DPM.0
-xxx
-xxx
-uuu
$12 - DPH.2 DPH.1 DPH.0
-xxx
-xxx
-uuu
$13 - LCDOFF HLM PAM
-100
-P00
-100
$14
AEC3
AEC2
AEC1
AEC0
0000
0000
0000
$15 PPULL O/S2 O/S1
-
000-
000-
000-
$16 - $19
-
-
-
-
----
----
----
$1A WDT
-
-
-
1---
1---
0---
$1B PACR.3 PACR.2 PACR.1 PACR.0
0000
0000
0000
$1C PBCR.3 PBCR.2 PBCR.1 PBCR.0
0000
0000
0000
$1D PCCR.3 PCCR.2 PCCR.1 PCCR.0
0000
0000
0000
$1E PDCR.3 PDCR.2 PDCR.1 PDCR.0
0000
0000
0000
$1F - - - -
----
----
----
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’.
P = 1 (Single solar supply application option disable) P = unchanged (Single solar supply application option enable).
4.2. Others Initial States:
Others
Program Counter (PC)
After any Reset
$000
CY Undefined
Accumulator (AC)
Undefined
Data Memory
Undefined
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부품번호상세설명 및 기능제조사
SH66L10A

2K 4-bit Microcontroller

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