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PDF SH66P12 Data sheet ( Hoja de datos )
| Número de pieza | SH66P12 | |
| Descripción | OTP 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH66P12
OTP 4-bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit microcontroller with
LCD driver
ROM: 2048 X 16 bits
RAM: 256 X 4 bits (Data memory)
Operation voltage: 2.5V - 5.4V
16 CMOS I/O pins
- CMOS or Open Drain (code option)
4 level subroutine nesting (including interrupts)
Two 8-bit timer/counter with pre-divider circuit
Oscillator warm-up timer
4 priority interrupt sources:
- External interrupt (falling edge)
- Timer0 interrupt
- Timer1 interrupt
- PortB interrupt (falling edge)
Oscillator
- 32.768KHz crystal or 262K RC (code option)
Instruction cycle time:
- 4/32.768KHz (≈ 122µs) for 32.768KHz OSC clock
- 4/262KHz (≈ 15µs) for 262KHz OSC clock
LCD driver:
- 4 X 26 (1/4 duty, 1/3 bias or 1/3 duty, 1/2 bias)
Two low power operation modes: HALT or STOP mode
Built-in alarm generator carrier frequency:
- 2KHz or 4KHz (code option)
Low power consumption (Iop < 10µA, 32.768KHz, 3V)
Bonding option for multi-code software
Available in CHIP FORM
General Description
SH66P12 is a single-chip microcontroller integrated with an SH6610C 4-bit CPU core, SRAM, timer, alarm generator, LCD
driver, I/O port, and program ROM.
Pad Configuration
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SSSSSSSSSS
E E E E E E E E E E CC
GGGGGGGGGGOO
1 1 1 2 2 2 2 2 2 2 MM
789012345612
38 37 36 35 34 33 32 31 30 29 28 27
39 26
40 25
41 24
42 23
43 22 B1
44 21
45 SH66P12 20
46 19
47 18
48 17
49 16
50 15
51 5
14
52 1 2 3 4 B0 6 7 8 9 10 11 12 13
COM3
COM4
OSCI
OSCO
GND
PORTD3
PORTD2
PORTD1
PORTD0
PORTC3
PORTC2
PORTC1
PORTC0
PORTB3
S
E
G
2
S
E
G
1
T
E
S
T
R
E
S
E
V
D
D
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
P
O
R
T
T AAAABBB
0123012
1 V2.2
1 page  
SH66P12
3. RAM
Built-in RAM contains of general-purpose data memory, LCD
RAM, and system register. Data memory, LCD RAM, and
system register can be direct accessed by in one instruction
cycle. Because of its static nature, the RAM can keep data
after the CPU enters STOP or HALT.
(a) Data memory, LCD RAM, and System register
The following is the memory allocation map:
$000 - $01F: System register and I/O
$020 - $11F: Data memory (256 X 4 bits divided into 2
banks)
$300 - $319: LCD RAM space (26 X 4 bits)
(b) Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPM (3-bits) and DPL
(4-bits). The addressing range can have 128 locations.
Pseudo index address (INX) is used to read or write Data
memory, and then RAM address bit9-bit0 comes from DPH,
DPM and DPL.
(c) Configuration of System Register
Address Bit 3
Bit 2
Bit 1
Bit 0
R/W
Description
$00
IEX
IET0
IET1
IEP R/W Interrupt enable flags
$01
IRQX
IRQT0 IRQT1
IRQP R/W Interrupt request flags
$02
-
T0M.2
T0M.1
T0M.0 R/W Bit0-2: Timer0 Mode register
$03
-
T1M.2
T1M.1
T1M.0 R/W Bit0-2: Timer1 Mode register
$04
T0L.3
T0L.2
T0L.1
T0L.0 R/W Timer0 load/counter register low nibble
$05
T0H.3
T0H.2
T0H.1
T0H.0 R/W Timer0 load/counter register high nibble
$06
T1L.3
T1L.2
T1L.1
T1L.0 R/W Timer1 load/counter register low nibble
$07
T1H.3
T1H.2
T1H.1
T1H.0 R/W Timer1 load/counter register high nibble
$08
PA.3
PA.2
PA.1
PA.0
R/W PORTA
$09
PB.3
PB.2
PB.1
PB.0
R/W PORTB
$0A
PC.3
PC.2
PC.1
PC.0
R/W PORTC
$0B
PD.3
PD.2
PD.1
PD.0
R/W PORTD
LPD Enable Control (LPD3 - 0):
$0C
LPD3
LPD2
LPD1
LPD0
W 0101: LPD Enable (Default);
1010: LPD Disable
$0D -
- B1 B0 R Bonding option
$0E
TBR.3
TBR.2
TBR.1
TBR.0 R/W Table Branch Register
$0F
INX.3
INX.2
INX.1
INX.0 R/W Pseudo index register
$10
DPL.3
DPL.2
DPL.1
DPL.0 R/W Data pointer for INX low nibble
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble
$12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble
Bit0: set PA.1, PA.2 as Alarm output
$13
O/S LCDOFF HLM
PAM
R/W
Bit1: HEAVY LOAD Mode
Bit2: LCD off or LCD on
Bit3: set LCD segment as output
$14
AEC3
AEC2
AEC1
AEC0 R/W Alarm Envelope Control
$15 - - - DUTY R/W Bit0: change LCD duty to 1/4 duty, 1/3 bias
$16 - $1F
-
-
-
- - Reserved
5
5 Page 
SH66P12
(b) Timer0 Interrupt
The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt
enable flag is enabled, then a timer interrupt service routine will start. This can also be used to wake CPU from HALT mode.
(c) Timer mode register
The timer can be programmed in several different prescaler ratios by setting Timer Mode register (TM0, TM1).
The 8-bit counter prescaler output pulses. The Timer Mode registers (TM0, TM1) are 3-bit registers used for the timer control as
shown in Table1 and Table 2. These mode registers select the input pulse sources into the timer.
Table 1. Timer0 Mode Register ($02)
TM0.2
0
0
0
0
1
1
1
1
TM0.1
0
0
1
1
0
0
1
1
TM0.0
0
1
0
1
0
1
0
1
Prescaler Divide Ratio
/211
/29
/27
/25
/23
/22
/21
/20
Clock Source
System clock
System clock
System clock
System clock
System clock
System clock
System clock
System clock
Table 2. Timer1 Mode Register ($03)
TM1.2
0
0
0
0
1
1
1
1
TM1.1
0
0
1
1
0
0
1
1
TM1.0
0
1
0
1
0
1
0
1
Prescaler Divide Ratio
/211
/29
/27
/25
/23
/22
/21
/20
Clock Source
System clock
System clock
System clock
System clock
System clock
System clock
System clock
System clock
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet SH66P12.PDF ] | |
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