Datasheet.kr   

SH66P14A 데이터시트 PDF




Sino Wealth에서 제조한 전자 부품 SH66P14A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 SH66P14A 자료 제공

부품번호 SH66P14A 기능
기능 OTP 4-bit Microcontroller
제조업체 Sino Wealth
로고 Sino Wealth 로고


SH66P14A 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 30 페이지수

미리보기를 사용할 수 없습니다

SH66P14A 데이터시트, 핀배열, 회로
SH66P14A
OTP 4-bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit microcontroller
OTPROM: 4096 X 16 bits
RAM: 512 X 4 bits (System & Data memory)
Operation voltage: 2.4V - 5.5V
8 CMOS bi-directional I/O pins
4-Level subroutine nesting (include interrupts)
One 8-bit auto re-load timer/counter
8-bit Base timer
Powerful interrupt sources:
- External interrupts ( INT0 )
- Internal interrupt (Timer0)
- Internal interrupt (Base Timer)
- Port's falling edge interrupt: PORTB ( INT1 )
LCD driver:
- 240 dots (1/8 duty 1/4 bias)
- 136 dots (1/4 duty 1/3 bias)
LCD used as scan output
Built-in dual tone PSG with one noise generator
2 Clock source
OSC: (code option)
- Crystal oscillator 32.768K
- RC oscillator: 262K
OSCX: (system register select)
- Ceramic oscillator 455K
- RC oscillator 1.8M or 2M
Instruction cycle time:
- 122.07µs for 32.768 KHz crystal
- 15.27µs for 262 KHz RC
- 8.79µs for 455KHz ceramic
- 2.22µs for 1.8 MHz RC
- 2µs for 2.0 MHz RC
Two low power operation mode: HALT and STOP
Low power consumption
Warm up timer for power on reset
General Description
SH66P14A is a single chip microcontroller integrated with SRAM, OTP ROM, Timer and Dual-tone PSG, LCD driver and I/O
port. This chip builds in a dual-oscillator to enhance the total chip performance.
Pad Configuration
S S S S S S S S S S S S S CC
EEEEEEEEEEEEE 87
GGGGGGGGGGGGG / /
1 1 2 2 2 2 2 2 2 2 2 2 3 SS
8 9 0 1 2 3 4 5 6 7 8 9 0 31 32
SEG17 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
SEG16 45
28 COM6/SEG33
SEG15 46
27 COM5/SEG34
SEG14 47
26 COM4
SEG13 48
25 COM3
SEG12 49
24 COM2
SEG11
SEG10
50
51
SH66P14A
23 COM1
22 OSCI
SEG9 52
21 OSCO
SEG8 53
GND 20
PC.0
SEG7 54
19 OSCXO
SEG6 55
18 OSCXI
SEG5 56
SEG4 57
17 PA.0
VDD
9 16 PA.1
58 1 2 3 4 5 6 7 8
10 11 12 13 14 15 PA.2
_
S S S V V V VT RPP P P P P
E E E L 1 2 3 E E C. B. B. B. B. A.
GGGC
321D
S S1 3 21 03
T
E
T
1 V2.1




SH66P14A pdf, 반도체, 판매, 대치품
SH66P14A
Functional Description
1. CPU
The CPU contains the following function blocks: Program
Counter, Arithmetic Logic Unit (ALU), Carry Flag,
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL), and Stack.
1.1. PC (Program Counter)
The Program Counter is used to address the 4K program
ROM. It consists of 12-bits: Page Register (PC11), and
Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5,
PC4, PC3, PC2, PC1, PC0).
The program counter normally increases by one (+1) with
every execution of an instruction except in the following
cases:
(1) When executing a jump instruction (such as JMP, BA0,
BC);
(2) When executing a subroutine call instruction (CALL);
(3) When an interrupt occurs;
(4) When the chip is at the INITIAL RESET mode.
The program counter is loaded with data corresponding to
each instruction.
The unconditional jump instruction (JMP) can be set at 1-bit
page register for higher than 2K.
1.2. ALU and CY
ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI,
SBI)
Decimal adjustment for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decision (BA0, BA1, BA2, BA3, BAZ, BC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow, which the
arithmetic operation generates. During an interrupt service
or call instruction, the carry flag is pushed into the stack and
restored back from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator
Accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with ALU, data transfers
between the accumulator and system register, LCD RAM, or
data memory can be performed.
1.4. Stack
A group of registers used to save the contents of CY & PC
(10-0) sequentially with each subroutine call or interrupt. It is
organized 13 bits X 4 levels. The MSB is saved for CY. 4
levels are the maximum allowed total for subroutine calls and
interrupts.
The contents of Stack are returned sequentially to the PC
with the return instructions (RTNI/RTNW). Stack is operated
on a first-in, last-out basis. This 4-level nesting includes both
subroutine calls and interrupts requests. Note that program
execution may enter an abnormal state if the number of calls
and interrupt requests exceeds 4, and the bottom of stack
will be shifted out.
2. OTPROM
The OTPROM can address 4096 words X 16 bits of program area from $000 to $FFF.
2.1. Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
Address
Instruction
Function
$000H
JMP Instruction
Jump to RESET service routine
$001H
$002H
JMP Instruction
JMP Instruction
Jump to INT0 service routine
Jump to Timer0 service routine
$003H
JMP Instruction
Jump to Base Timer service routine
$004H
JMP Instruction
Jump to INT1 service routine
2.2. Table Data Reference
Table Data can be stored in program memory and can be referenced by using Table Branch (TJMP) and Return Constant
(RTNW) instructions. The Table Branch Register (TBR) and Accumulator (AC) are placed by an offset address in program
ROM. TJMP instruction branches into address ((PC11 - PC8) X (28) + (TBR, AC)). The address is determined by RTNW to
return look-up value into (TBR, AC). ROM code bit7-bit4 is placed into TBR and bit3-bit0 into AC.
4

4페이지










SH66P14A 전자부품, 판매, 대치품
SH66P14A
4. Oscillator Circuit
4.1. Circuit Configuration
SH66P14A has two on-chip oscillation circuits OSC and OSCX.
OSC is a low frequency crystal (Typ. 32.768KHz) or RC (Typ.262KHz) determined by the code option. This is designed for low
frequency operation. OSCX also has two types: ceramic (Typ.455KHz) or RC (1.8M or 2MHz) determined by software option. It
is designed for high frequency operation.
It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low
operation clock. At starting of reset initialization, OSC starts oscillation and OSCX is turned off. Immediately after reset
initialization, the OSC clock is automatically selected as the system clock input source.
OSCI
Low Frequency
OSCO Clock Oscillator
OSCXI
High Frequency
OSCXO Clock Oscillator
System clock
Source Selector
& Switching control
Base Timer
System clock
Generator
CPU Clock
OSCXO
Figure 1. Oscillator Block Diagram
OSCX turn off
OSCX turn on
OSCO
SYS CLOCK
High
frequency
operation
Low frequency operation
Warm-up time
Switch from OSCX to OSC
High frequency operation
Switch from OSCX to OSC
Figure 2. Timing of system Clock Switching
4.2. OSC Oscillation
The OSC generates the basic clock pulses that provide the CPU and peripherals (Timer0, LCD) with an operating clock.
(1) OSC Crystal Oscillator Type
CPU STOP
OSCI
TO CPU
32768Hz XTL
OSCO
RF
5-6p
RO
7

7페이지


구       성 총 30 페이지수
다운로드[ SH66P14A.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
SH66P14A

OTP 4-bit Microcontroller

Sino Wealth
Sino Wealth

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵