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PDF SH67L17A Data sheet ( Hoja de datos )
| Número de pieza | SH67L17A | |
| Descripción | 24K 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH67L17A
24K 4-bit Micro-controller with LCD Driver
Features
SH6610D-based single-chip 4-bit micro-controller with LCD
driver
ROM: 24K X 16bits
RAM: 4136 X 4bits (Excluding LCD RAM)
- 43 System Control Register
- 4093 Data memory
- 180 LCD RAM
Operation Voltage: 1.2V - 1.7V (Typical 1.5V)
Built-in 1.5V Regulator (Input Voltage: 1.6V - 3.5V)
24 CMOS Bi-directional I/O Pins (including 8 shared with
SEG/COM pins)
8-Level Stack (Including Interrupts)
One 8-bit Base Timer
One 8-bit Auto Reloaded Timer/Counter
Warm-Up Timer
Powerful Interrupt Sources:
———
- External interrupt (INT share with PORTA.0)
- Timer0 interrupt
- Base timer interrupt
- PORTB & PORTC interrupts (Falling edge)
2 Clock Sources
OSC: (Code Option selects the type of OSC)
- Crystal Oscillator: 32.768kHz
- RC Oscillator: 131kHz
OSCX:
- RC oscillator: 500kHz (ROSCX)
Instruction Cycle Time (4/fOSC)
Built-in Alarm Generator
Two Low Power Operation Modes: HALT And STOP
Special HALT/STOP mode
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) (Code Option)
- RESET0 & RESET1
LCD Driver:
- 60SEG X 9COM (1/9 Duty, 1/4 Bias)
- 60SEG X 5COM (1/5 Duty, 1/4 Bias)
- 60SEG X 5COM (1/5 Duty, 1/3 Bias)
- 60SEG X 4COM (1/4 Duty, 1/3 Bias)
Built-in Pull-high Resistor For PORTA - PORTF
Built-in Voltage Fourfold/Tripler Charge Pump Circuit
ROM Data Read Table Function (RDT)
RAM common space in every RAM bank
Low power consumption
Available in CHIP FORM
General Description
SH67L17A is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, Base Timer, Timer0,
Alarm generator, LCD driver, I/O ports, and voltage pump circuit. The SH67L17A is suitable for scientific calculator application.
1 V1.0
1 page  
SH67L17A
Functional Description
1. CPU
The CPU contains the following functional blocks:
Program Counter (PC), Arithmetic Logic Unit (ALU), Carry
Flag (CY), Accumulator, Table Branch Register, Data Pointer
(INX, DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM, SBC,
SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code Bit7-Bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory. Pointer
address is located in register DPH (3-bit), DPM (3-bit) and
DPL (4-bit). The addressing range is 000H - 3FFH. Pseudo
index address (INX) is used to read or write Data memory,
then RAM address Bit9 - Bit0 which comes from DPH, DPM
and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 8 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC by the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
5
5 Page 
SH67L17A
5. System Clock and Oscillator
The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals.
System clock = fOSC/4
5.1. Instruction Cycle Time
(1) 4/32.768kHz (≈ 122.07µs) for 32.768kHz oscillator.
(2) 4/131kHz (≈ 30.53µs) for 131kHz RC oscillator.
(3) 4/500kHz (= 8µs) for 500kHz RC oscillator.
5.2. Circuit Configuration
SH67L17A has two on-chip oscillation circuits OSC and OSCX.
OSC is a low frequency crystal (Typ. 32.768kHz) or RC (Typ. 131kHz) determined by the code option. This is designed for low
frequency operation. OSCX has one type: RC (500kHz). It is designed for high frequency operation.
It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low operation
clock. At starting of reset initialization, OSC starts oscillation and OSCX is turned off. Immediately after reset initialization, the
OSC clock is automatically selected as the system clock input source.
VDD
OSCI
131kHz RC
VDD
Low Frequency
Clock Oscillator
OSCXI
High Frequency
500kHz RC
Clock Oscillator
System clock
Source Selector
& Switching control
System clock
Generator
CPU Clock
Figure 1. Oscillator Block Diagram
OSCXO
OSCX turn off
OSCX turn on
OSCO
SYS CLOCK
High
frequency
operation
Low frequency operation
Switch from OSCX to OSC
High frequency operation
Switch from OSC to OSCX
Figure 2. Timing of System Clock Switching
5.3. OSC Oscillator
The OSC generates the basic clock pulses that provide the CPU and peripherals (Base timer, LCD) with an operating clock.
(1) OSC RC oscillator
(2) OSC Crystal oscillator
OSCI
ROSC
VDD
OSCI
C1
Crystal
OSCO
C2
External ROSC RC
5.4. OSCX Oscillator
OSCX RC oscillator
OSCXI
ROSCX
VDD
External ROSCX RC
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH67L17A.PDF ] | |
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