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PDF SH67L18 Data sheet ( Hoja de datos )
| Número de pieza | SH67L18 | |
| Descripción | 8K 4-bit Low Power Micro-controller | |
| Fabricantes | Sino Wealth Microelectronic | |
| Logotipo |  |
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SH67L18
8K 4-bit Low Power Micro-controller with LCD Driver
Features
SH6610D-based single-chip 4-bit micro-controller with
LCD driver
ROM: 8K X 16 bits
RAM: 768 X 4 bits
- 32 System Control Register
- 736 Data memory
- 195 bits LCD RAM
Operation Voltage:
fOSCX = 300kHz, VDD = 1.2V - 1.7V (Typical 1.5V)
fOSCX = 800kHz, VDD = 1.3V - 1.7V
16 CMOS Bi-directional I/O pads (including 4 input only
pads)
8-Level Stack (Including Interrupts)
Powerful Interrupt Sources:
- External interrupt (Low active)
- Base Timer interrupt
- PORTB, PORTC & PORTD interrupts (Low active)
Oscillator (Code Option):
OSCX:
- RC oscillator:
- RC oscillator:
300kHz
800kHz
Base timer clock source (Code Option):
OSC:
- Crystal Oscillator:
- RC oscillator:
32.768kHz
32kHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT And STOP
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) (Code Option)
LCD Driver:
40SEG X 4COM (1/4 Duty, 1/3 Bias)
39SEG X 5COM (1/5 Duty, 1/3 Bias)
Built-in Voltage Tripler Charge Pump Circuit
Built-in Alarm Generator
Single solar supply application (Code Option)
Low power consumption
Read Rom Data Table function (RDT)
Bonding option for multi-code software
Available in CHIP FORM
General Description
SH67L18 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core; RAM, ROM, Base Timer, Alarm
generator, LCD driver, I/O ports, and voltage tripler charge pump circuit. The SH67L18 is suitable for fraction calculator
application.
1 V2.0
1 page  
SH67L18
Functional Description
1. CPU
The CPU contains the following functional blocks:
Program Counter (PC), Arithmetic Logic Unit (ALU), Carry
Flag (CY), Accumulator, Table Branch Register, Data
Pointer (INX, DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4 Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code Bit7-Bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM
(3-bit) and DPL (4-bit). The addressing range is
000H--3FFH. Pseudo index address (INX) is used to read or
write Data memory, then RAM address Bit9 - Bit0 which
comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 8 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC by the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU entering STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register: $000 - $01F
Data memory: $020 - $2FF, $328 - $32F, $358 - $35F
LCD RAM space: $300 - $327, $330 - $357
RAM bank table:
Bank0
B=0
Bank1
B=1
Bank2
B=2
Bank3
B=3
Bank4
B=4
Bank5
B=5
Bank 6
B=6
$020 - $07F $080 - $0FF $100 - $17F $180 - $1FF $200 - $27F $280 - $2FF $300 - $37F
Where, B: RAM bank bit use in instructions.
5
5 Page 
SH67L18
PORTB, PORTC and PORTD Interrupt
The PORTB, PORTC and PORTD are used as the port interrupt sources. Following is the port interrupt function block-diagram.
IEP
PB.n
PC.n
PD.n
PBCR.n
PCCR.n
PDIE.n
Note: n = 0, 1, 2, 3
Low level
Detector
Port Interrupt
IRQP
Port Interrupt (PORTB, PORTC & PORTD interrupts) PROGRAMMING NOTES:
If user wants to generate an interrupt when a low level emerges on the port, the following must be executed.
1. Set the port as input port, fill port data register with “1” and avoid port floating.
2. Pull-high the port (Use external pull-high resistance or set PULLEN to “1” and write “1” to the port data register).
In order to correctly return from the port interrupt-processing subroutine, the low level applying on the port must be
released before the relative IRQ flag clearing and IE resetting. Otherwise, it is possible to reenter the active interrupt.
Since PORTD.3-0 can be used as input ports only, there are another interrupts enable control registers for each I/O in PORTD.
System Register $1D: Port Interrupt Enable Flags Register
Address Bit 3
Bit 2
Bit 1
Bit 0 R/W
Remarks
$1D PDIEN.3 PDIEN.2 PDIEN.1 PDIEN.0 R/W PORTD interrupt enable control register
PDIEN.n, (n = 0, 1, 2, 3)
0: Disable port interrupt. (Power on initial)
1: Enable port interrupt.
External Interrupt (PORTA.0):
If user wants to generate an external interrupt when a low level emerges on PORTA.0, the following must be executed.
1. Set PORTA.0 as input port, fill port data register with “1” and avoid port floating.
2. Pull-high PORTA.0 (Use external pull-high resistance or set PULLEN to “1”).
In order to correctly return from the external (PORTA.0) interrupt-processing subroutine, the low level applying on the
PORTA.0 must be released before the relative IRQ flag clearing and IE resetting. Otherwise, it is possible to reenter
the active interrupt.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH67L18.PDF ] | |
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