PDF SH67P847 Data sheet ( Hoja de datos )

Número de pieza	SH67P847
Descripción	OTP 1K 4-bit Microcontroller
Fabricantes	Sino Wealth
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No Preview Available ! SH67P847 OTP 1K 4-bit micro-controller with 10-bit SAR ADC Features SH6610C-Based Single-Chip 4-bit Micro-Controller With 10-bit SAR ADC OTP ROM: 1K X 16bits RAM: 124 X 4bits - 28 System Control Registers - 96 Data Memory Operation Voltage: - fOSC = 16MHz, VDD = 3.3V - 5.5V 6 CMOS Bi-Directional I/O Pins 4-Level Stack (Including Interrupts) One 8-bit Auto Re-Loaded Timer Warm-Up Timer Powerful Interrupt Sources: - A/D Interrupt - Timer0 Interrupt - External Interrupts: PORTA.3 (Falling Edge) Oscillator - Internal RC Oscillator: 16MHz Instruction Cycle Time (16/fOSC) Two Low Power Operation Modes: HALT And STOP Reset - Built-in Power-on Reset (POR) - Built-in Low Voltage Reset (LVR) (Code Option) - Built-in Watchdog Timer (WDT) (Code Option) 4 Channels 10-bit Resolution Analog/Digital Converter (ADC) 1 Channels 9-bit PWM Output OTP Type/Code Protection 8-pin SOP package available General Description SH67P847 is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, RAM, ROM, timer, ADC, high speed PWM output, watch dog timer, low voltage reset. The SH67P847 is suitable for charger application. Pin Configuration PORTB.1/PWM PORTA.3/VPP GND PORTA.0/VREF/AN0/SDA 1 2 3 4 8 PORTB.0/AN3 7 PORTA.2/AN2/SCK 6 VDD 5 PORTA.1/AN1 1 V2.0 1 page SH67P847 2.2. Configuration of System Register Address Bit 3 Bit 2 Bit 1 Bit 0 R/W Remarks $00 IEAD IET0 - IEP R/W Interrupt enable flags register $01 IRQAD IRQT0 - IRQP R/W Interrupt request flags register $02 - T0M.2 T0M.1 T0M.0 R/W Bit2-0: Timer0 Mode register $03 T0L.3 T0L.2 T0L.1 T0L.0 R/W Timer0 load/counter low nibble register $04 T0H.3 T0H.2 T0H.1 T0H.0 R/W Timer0 load/counter high nibble register $05 PA.3 PA.2 PA.1 PA.0 R/W PORTA data register $06 - - PB.1 PB.0 R/W PORTB data register $07 VREFS CH1 $08 ACR3 ACR2 $09 GO/ DONE TADC1 $0A A2 A1 CH0 ACR1 TADC0 A0 ADCON ACR0 ADCS - Bit0: ADC module operate control register R/W Bit2-1: ADC channel control register Bit3: ADC reference voltage control register R/W Bit3 - 0: ADC port configuration register Bit0: ADC conversion time control register R/W Bit1-0: ADC clock period control register Bit3: ADC status flag register R ADC data low nibble register $0B A6 A5 A4 A3 R ADC data medium nibble register $0C - A9 A8 A7 R ADC data high nibble register $0D - - - - R/W Reserved $0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch register $0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register $10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble register $11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble register $12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble register $13 PACR.3 PACR.2 PACR.1 PACR.0 R/W PORTA input/output control register $14 - - PBCR.1 PBCR.0 R/W PORTB input/output control register Bit0: PWM output control register $15 PWMS TCK1 TCK0 PWM_EN R/W Bit2-1: PWM clock source control register Bit3: PWM output mode control register $16 PP.3 PP.2 PP.1 PP.0 R/W PWM period low nibble register $17 PP.7 PP.6 PP.5 PP.4 R/W PWM period high nibble register $18 - - - PDF.0 R/W PWM duty fine tune register $19 PD.3 PD.2 PD.1 PD.0 R/W PWM duty low nibble register $1A PD.7 PD.6 PD.5 PD.4 R/W PWM duty high nibble register $1B - PPACR.2 PPACR.1 PPACR.0 R/W PORTA pull-high control register $1C - - PPBCR.1 PPBCR.0 R/W PORTB pull-high control register $1D - - - - - Reserved $1E - WDT WDT.2 - WDT.1 - WDT.0 R/W Bit2-0: Watchdog timer control register - R Bit3: WDT overflow flag register $1F - - - - - Reserved 5 5 Page SH67P847 7. Timer 7.1. Timer0 SH67P847 has one 8-bit timer. The timer/counter has the following features: - 8-bit up-counting timer/counter. - Automatic re-load counter. - 8-level prescaler. - Interrupt on overflow from $FF to $00. The following is a simplified timer block diagram. System clock 4tOSC SYNC Prescaler 8-BIT COUNTER TM.2 TM.1 TM.0 The low-order digit should be written first, and then the high-order digit. The timer counter is automatically loaded with the contents of the load register when the high order digit is written or counter counts overflow from $FF to $00. Timer Load Register: The register H controls the physical READ and WRITE operations. Please follow these steps: Write Operation: Low nibble first High nibble to update the counter Read Operation: High nibble first Low nibble followed. The timers provide the following functions: - Programmable interval timer function. - Read counter value. 7.1.1. Timer0 Configuration and Operation The Timer0 consist of an 8-bit write-only timer load register (TL0L, TL0H) and an 8-bit read-only timer counter (TC0L, TC0H). Each of them has both low-order digits and high-order digits. Writing data into the timer load register (TL0L, TL0H) can initialize the timer counter. Load Reg. L Load Reg. H 8-bit timer counter Latch Reg. L 7.1.2. Timer0 Mode Register The Timer0 can be programmed in several different prescalers by setting the Timer0 Mode register (T0M). The clock source pre-scale by the 8-level counter first, then generate the output plus to timer counter. The Timer Mode registers (T0M) are 3-bit registers used for the timer control as shown in Table 1. Table 1. Timer0 Mode Register ($02) T0M.2 0 0 0 0 1 1 1 1 T0M.1 0 0 1 1 0 0 1 1 T0M.0 0 1 0 1 0 1 0 1 Prescaler Divide Ratio /211 /29 /27 /25 /23 /22 /21 /20 Clock Source System clock System clock System clock System clock System clock System clock System clock System clock 11 11 Page

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