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PDF SH69P21 Data sheet ( Hoja de datos )
| Número de pieza | SH69P21 | |
| Descripción | OTP 1K 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH69P21
OTP 1K 4-bit Micro-controller
Features
SH6610C-based single-chip 4-bit micro-controller
OTP ROM: 1K X 16 bits
RAM: 88 X 4 bits
- 24 System control register
- 64 Data memory
Operation Voltage: 2.4V - 5.5V
- fOSC = 30kHz - 4MHz, VDD = 2.4V - 5.5V
- fOSC = 4MHz - 8MHz, VDD = 4.5V - 5.5V
11CMOS bi-directional I/O pins and 1CMOS input pin
4-Level Stack (Including Interrupts)
One 8-bit auto re-loaded Timer/Counter
Warm-up Timer
Powerful Interrupt Sources:
- External interrupt0:
PORTA.0 (Falling/Rising/Double Edge)
- Timer0 interrupt (Timer0)
- External Interrupts: PORTB (Falling Edge)
Oscillator: (Code Option)
- Crystal oscillator:
32.768kHz, 400kHz - 8MHz
- Ceramic resonator: 400kHz - 8MHz
- External RC oscillator: 400kHz - 8MHz
- Internal RC oscillator: 8MHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT And STOP
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR)
Two-level low voltage reset (LVR) (Code Option)
SOP 14/8, SSOP10 Package
General Description
SH69P21 is a single-chip 4-bit micro-controller. This device integrates a SH6610C CPU core, RAM, ROM, PWM, Timer,
I/O ports and 8MHz internal RC. The SH69P21 is suitable for alarm or home appliance application.
1 V2.0
1 page  
SH69P21
Function Description
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag
(CY), Accumulator, Table Branch Register, Data Pointer
(INX, DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The
ALU provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service
or CALL instruction, the carry flag is pushed into the stack
and recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of
the arithmetic logic unit. In conjunction with the ALU, data
is transferred between the accumulator and system
register, or data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are
placed by an offset address in program ROM. TJMP
instruction branch into address ((PC11 - PC8) X (28) +
(TBR, AC)). The address is determined by RTNW to return
look-up value into (TBR, AC). ROM code bit7 - bit4 is
placed into TBR and bit3-bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM
(3-bit) and DPL (4-bit). The addressing range is 000H -
3FFH. Pseudo index address (INX) is used to read or write
Data memory, then RAM address bit9 - bit0 which comes
from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents
of CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into
13 bits X 4 levels. The stack is operated on a first-in,
last-out basis and returned sequentially to the PC with the
return instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 4 levels. If the number of calls and
interrupt requests exceeds 4, then the bottom of stack will
be shifted out, that program execution may enter an
abnormal state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep
data after the CPU entering STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System Register: $000 - $01F
Data Memory: $020 - $05F
5
5 Page 
SH69P21
6. Timer0
The timer/counter has the following features:
- 8-bit up-counting timer/counter
- Automatic re-loads counter
- 8-level prescaler
- Internal and external clock select
- Interrupt on overflow from $FF to $00
- Edge select for external event
The following is a simplified timer block diagram:
System
clock
T0 EOR
T0E
MUX
T0S T0GO
tOSC SYNC
Prescaler
TM.2 TM.1 TM.0
8-BIT
COUNTER
6.1. Timer0 Configuration and Operation
The Timer0 consists of an 8-bit write-only timer load
register (TL0L, TL0H), and an 8-bit read-only timer counter
(TC0L, TC0H). Each of them has low order digits and high
order digits. Writing data into the timer load register (TL0L,
TL0H) can initialize the timer counter.
The low-order digit should be written first, and then the
high-order digit. The timer counter is automatically loaded
with the contents of the load register when the high order
digit is written or counter counts overflow from $FF to $00.
Timer Load Register: Since register H would control the
physical READ and WRITE operations.
Please follow these steps:
Write Operation:
Low nibble first;
High nibble to update the counter.
Read Operation:
High nibble first;
Low nibble followed.
Load Reg. L Load Reg. H
8-bit timer counter
Latch Reg. L
6.2. Timer0 Mode Register
The timer can be programmed in several different prescalers by setting Timer Mode register (T0M).
The clock source pre-scale by the 8-level counter first, then generate the output plus to timer counter. The Timer Mode
registers (T0M) are 3-bit registers used for the timer control as shown in Table 1.
Table 1. Timer0 Mode Register ($02)
T0M.2
0
0
0
0
1
1
1
1
T0M.1
0
0
1
1
0
0
1
1
T0M.0
0
1
0
1
0
1
0
1
Prescaler Divide Ratio
/211
/29
/27
/25
/23
/22
/21
/20
Clock Source
System clock/T0
System clock/T0
System clock/T0
System clock/T0
System clock/T0
System clock/T0
System clock/T0
System clock/T0
Systems Register $1C: (T0)
Address Bit 3
$1C -
-
-
-
-
-
-
Bit 2
T0GO
X
X
X
X
0
1
Bit 1
T0S
X
X
0
1
X
X
Bit 0
T0E
0
1
X
X
X
X
R/W
R/W
Bit0: T0 signal edge
Bit1: T0 signal source
Remarks
R/W Increment on low-to-high transition T0 pin
R/W Increment on high-to-low transition T0 pin
R/W Used as PORTA.2, Timer0 source is system clock
R/W Used as T0 input, Timer0 source is T0 input clock
R/W Timer0 counter disable
R/W Set “1” start Timer0, T0GO = 1 when Timer0 is running
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SH69P21.PDF ] | |
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