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PDF SH69P561 Data sheet ( Hoja de datos )
| Número de pieza | SH69P561 | |
| Descripción | OTP/MASK 4K 4-bit Micro-controller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH69P561/K561
OTP/MASK 4K 4-bit Micro-controller With LCD Driver & 8-bit SAR ADC
Features
SH6610D-Based Single-Chip 4-bit Micro-Controller With
LCD Driver & 8-bit SAR ADC
OTP ROM: 4K X 16 bits (SH69P561)
MASK ROM: 4K X 16 bits (SH69K561)
RAM: 274 X 4bits
- 58 System control register
- 216 Data memory
- 72 bits LCD RAM
Operation Voltage:
- fOSC = 32.768kHz - 4MHz, VDD = 2.4V - 5.5V
- fOSC = 4MHz - 8MHz, VDD = 4.5V - 5.5V
15 CMOS Bi-directional I/O Pins
8-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Loaded Timer/Counter
Warm-Up Timer
Powerful Interrupt Sources:
- A/D Interrupt
- Timer0 Interrupt
- Timer1 Interrupt
- External Interrupts: PORTB (Rising/Falling Edge)
2 Clock Oscillator
OSC:
- Crystal Oscillator: 32.768kHz
- RC Oscillator: 262kHz
OSCX:
- Ceramic/Crystal Oscillator: 400kHz - 8MHz
- RC Oscillator: 400kHz - 8MHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT And STOP
Reset
- Built-in Watchdog Timer (WDT) (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) (Code Option)
LCD Driver:
18SEG X 4COM (1/4 duty, 1/3 bias)
2 Channels 10-bit PWM output
5 Channels 8-bit Resolution Analog/Digital Converter
(ADC)
Built-in Pull-high/Pull-low Resistor for PORTA - PORTE
Built-in Alarm Generator
Built-in Electroluminescent Light (EL-light) Driver
ROM Data Read Table function
Zero Cross Detect function for AC Power Line
LCD shared as LED matrix (Code Option)
LCD SEG 9-28 shared with scan output
OTP type & Code Protect (SH69P561)
MASK type (SH69K561)
44-pin QFP package
General Description
SH69P561/69K561 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer, LCD
driver, I/O ports, EL-light driver, watchdog timer, 5 channels 8-bit ADC, alarm generator, low voltage reset, 2 channels 10-bit
high speed PWM output, zero cross detect function. This chip builds in a dual-oscillator to enhance the total chip performance.
SH69P561/69K561 is suitable for the home appliance application.
1 V2.1
1 page  
SH69P561/K561
Functional Descriptions
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code bit7-bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM
(3-bit) and DPL (4-bit). The addressing range is
000H--3FFH. Pseudo index address (INX) is used to read or
write Data memory, then RAM address bit9 - Bit0 which
comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 8 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC with the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU enters STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $027, $380 - $391
Data memory: $028 - $0FF
LCD RAM space: $304 - $319, $35C - $369
RAM Bank Table:
Bank 0
B=0
Bank 1
B=1
Bank 6
B=6
Bank 7
B=7
$028 - $07F
$080 - $0FF
$300 - $37F
$380 - $3FF
Where, B: RAM bank bit use in instructions
5
5 Page 
SH69P561/K561
5. System Clock and Oscillator
The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on-chip peripherals.
System clock = fOSC/4
5.1. Instruction Cycle Time
(1) 4/32.768kHz (≈ 122µs) for 32.768kHz oscillator.
(2) 4/262kHz (≈ 15.27µs) for 262kHz oscillator.
(3) 4/455kHz (≈ 8.79µs) for 455kHz oscillator.
(4) 4/4MHz (= 1µs) for 4MHz oscillator.
(5) 4/8MHz (= 0.5µs) for 8MHz oscillator.
5.2. Circuit Configuration
SH69P561/69K561 has two on-chip oscillation circuits: the OSC and the OSCX.
The OSC is a low frequency crystal (Typ. 32.768kHz) or RC (Typ.262kHz) determined by the code option. This is designed for
low frequency operation. The OSCX also has two types: ceramic/crystal (400k to 8MHz) or RC (400k to 8MHz) to be determined
by the code option. It is designed for high frequency operation.
It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low
operation clock. At the start of Power on reset, Pin reset and low power reset initialization, the OSC starts oscillation and OSCX
is turned off. But at the start of WDT reset initialization, the OSC starts oscillation and the OSCX remains the original state.
Immediatly after reset initialization, the OSC clock is automatically selected as the system clock input source.
OSCI
Low Frequency
OSCO Clock Oscillator
OSCXI
High Frequency
OSCXO Clock Oscillator
System clock
Source Selector
& Switching control
System clock
Generator
CPU Clock
Figure 1. Oscillator Block Diagram
OSCXO
OSCX turn off
OSCX turn on
OSCO
SYS CLOCK
High
frequency
operation
Low frequency operation
Switch from OSCX to OSC
High frequency operation
Switch from OSC to OSCX
Figure 2. Timing of System Clock Switching
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH69P561.PDF ] | |
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