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PDF SH38200 Data sheet ( Hoja de datos )
| Número de pieza | SH38200 | |
| Descripción | 315/433/868/915MHz FSK Transceiver | |
| Fabricantes | SINO WEALTH | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH38200 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SH38200
Preliminary
315/433/868/915MHz FSK Transceiver
Features
Frequency bands: 315/433/868/915MHz
Programmable RF output power: up to 15dBm
Low power consumption:
RX:12mA, TX:20mA@0dBm
Supply voltage 2.2 ~ 3.6V
Programmable data rate up to 150kbps
No external SAW Filter
Optional RTC function
On chip 8-bit ADC
Integrated temperature sensor
General Description
RSSI (Received Signal Strength Indicator)
Programmable channel filter bandwidth
Programmable carrier sense indicator
RX clock recovery
Frame synchronization recognition
Optional FEC/CRC/data whitening
Optional Manchester Data
64 bytes TX/RX FIFO buffer
Extended FIFO up to 256 bytes
Small 5x5 mm QFN32 package
SH38200 is a monolithic CMOS integrated circuit for wireless applications in 315/433/868/915MHz ISM band. The device is
provided in a 32-lead plastic QFN5X5 packaging and is designed as a complete FSK transceiver up to 150kbps data rate.
Typical Applications
Wireless data communication
Remote control
Keyless entry
Home automation
Wireless toy
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Pin Descriptions (I: input; O: output; OD: open drain output)
Pin No.
Symbol
Function Description
SH38200
1
RSSI
O RSSI bypass. Connect to external capacitor.
2
VSS
I Analog ground.
3 RFI I RF input.
4
VSS
I Analog ground.
5
RFO
O RF output.
6
VSS
I Analog ground.
7
VSS
I Analog ground.
8
VDD_VCO
I VCO Supply voltage.
9
VCON
I VCO inductor negative connection pin
10 VCOP I VCO inductor positive connection pin
11 VT I Control voltage of VCO
12
CPO
O Charge-pump output. This pin charges external capacitor to adjust VCO frequency.
13 VDD_PLL I PLL Supply voltage.
14 XO I Crystal oscillator node 2. Connect to external feedback capacitor.
15 XI I Crystal oscillator node 1. Connect to external feedback capacitor.
16
VDD_DIG
O Digital supply voltage. Connect to bypass capacitor.
17 SCS I SPI chip select. Active low.
18 SCK I SPI/FIFO clock.
19
SDIO
IO SPI/FIFO data.
20 DIO IO Bi-directional pin for direct mode. DATA input/output for TX/RX
21
CKO
O Clock out. Can be configured to RCK (RX recovery clock) or DCK (TX data clock).
22
IRQ
O
Interrupt request. Can be configured to CD (carrier detect), SYNC (RX frame sync) or
FP (FIFO packet).
23 TRS I TX/RX mode select. 0: RX, 1: TX.
24 TRE I TX/RX mode enable pin. Active high.
25 PWR_ON I Chip power on pin. Active high.
26 REG_IN I 3.3V supply voltage input pin.
27
RTCO
O 32KHz clock output.
28 XO_32K I 32KHz crystal oscillator node 2. Connect to external feedback capacitor.
29 XI_32K I 32KHz crystal oscillator node 1. Connect to external feedback capacitor.
30
BP_BG
O Bandgap bypass pin. Connect to external capacitor.
31
VDD_A
O Analog Supply voltage. Connect to bypass capacitor.
32 ADC_IN I External input for on-chip ADC.
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SH38200
R/W W W W W W W W W W W W W W W W
Reset 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1
FEP [7:0]: TX/RX FIFO end pointer in byte. FIFO mode packet stops when extended FIFO pointer= FEP [7:0]+1.
PSA [5:0]: TX FIFO packet start address in byte.
FPM [1:0]: TX/RX FIFO pointer margin threshold.
W
1
Setting
[00]
[01]
[10]
[11]
Bytes in TX FIFO
4
8
12
16
Bytes in RX FIFO
60
56
52
48
Address 0Ch: Code control
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
Name
WS6 WS5 WS4 WS3 WS2 WS1 WS0 MCS WHTS FECS CRCS IDL
R/W W W W W W W W W W W W W
Reset
0101010 00 00 1
PML [1:0]: Preamble length= PML+1 bytes.
IDL: ID length. 0: 2 bytes, 1: 4 bytes.
CRCS: CRC select. 1: Select. The CRC is CCITT-16 CRC.
FECS: FEC select. 1: Select. The FEC is (7, 4) Hamming code.
WHTS: Data whitening select. 1: Select. The data is whitening by multiplying PN7.
MCS: Manchester code select. 1: Select.
WS [6:0]: Whitening seed.
10
PML1 PML0
WW
01
Address 0Dh: Pin Control
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
PCS IRQI IRQ1 IRQ0 IRQE CKOI CKO1 CKO0 CKOE SCKI
R/W
WWWWWWWWWW
Reset
0000000101
SCKI: SPI clock invert. 1: Invert.
CKOE: CKO pin output enable. 0: High Z, 1: Enable.
CKO [1:0]: CKO select.
[00]: BCK (bit clock).
[01]: MRCK (modulation rate).
[10]: FPF (FIFO pointer flag).
[11]: Reversed.
When Manchester code is selected, BCK is the bit clock of Manchester code that equals half modulation rate. In
such case, BCK will appear after TX modulation start in TX mode or internal frame sync in RX mode. On the other
hand, BCK equals modulation rate.
When [11] selected, the output is the logic OR of EOP, EOVBC, EOFBC, EOADC and OKADC.
CKOI: CKO invert. 1: Invert.
IRQE: IRQ pin output enable. 0: High Z, 1: Enable.
IRQ [1:0]: IRQ function select.
TX state
[00] WPLL state & TX state(WTR)
[01] End of Access code (EOAC)
[10] TX modulation enable (TMEO)
[11] None
RX state
WPLL state & RX state(WTR)
Access code matched (FSYNC)
carrier detected (CD)
External FSYNC input ( for direct mode)
When IRQ set to [11] and direct mode is selected, the internal frame sync function will be disabled. In such case, it is
recommended that user assure frame sync signal to this input to get better DC estimation of demodulation.
IRQI: IRQ output invert. 0: normal, 1: Invert.
PCS: TRE and TRS pin control. 0: Register control, 1: Pin control.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH38200.PDF ] | |
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