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PDF SH67P93 Data sheet ( Hoja de datos )
| Número de pieza | SH67P93 | |
| Descripción | 24K OTP 4-bit Micro-Controller | |
| Fabricantes | SINO WEALTH | |
| Logotipo |  |
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SH67P93
24K OTP 4-bit Micro-Controller with LCD Driver
Feature
SH6610D-Based Single-Chip 4-bit Micro-Controller
OTPROM: 24K X 16 bits
RAM: 5784 X 4 bits
- 48 bytes System Control Register
- 5536 bytes Data Memory
- 200 bytes LCD RAM
Operation Voltage: 2.4V - 3.6V
23 CMOS Bi-directional I/O pads (15 shared with LCD
Segments)
12 Segments of LCD Shared with Scan Output port
8-Level Stack (including interrupts)
Two 8-bit Timer/Counter
Powerful Interrupt Sources
- External Interrupt (PORTA.0 Rising/Falling edge)
- Timer0 Interrupt
- Timer1 Interrupt
- External Interrupts: PORTB, PORTC and PORTD
(Falling edge)
LCD Driver
- 50 Seg X 16 Com (1/16 duty 1/4 bias or 1/5 bias)
- 50 Seg X 8 Com (1/8 duty 1/4 bias or 1/5 bias)
Oscillator (Code Option)
OSC
- Crystal Oscillator 32.768kHz
- RC Oscillator: 262kHz
OSCX
- Ceramic Resonator 3.58MHz/Crystal Oscillator 3.579545MHz
- RC oscillator 1.8MHz
Instruction Cycle Time
- 122.07µs for 32.768kHz crystal
- 15.27µs for 262 kHz RC
- 2.22µs for 1.8 MHz RC
- 1.1µs for 3.58MHz ceramic
Two Low Power Operation Modes: HALT and STOP
Warm-up Timer for Power-On Reset (POR)
Watchdog Timer
DTMF/FSK Generator
Available In CHIP FORM and Package
General Description
SH67P93 is a single-chip 4-bit micro-controller. The device integrates a SH6610D CPU core, RAM, OTP ROM, Timer, LCD
driver, I/O port, DTMF/FSK Generator and FSK/DTMF/CAS decoder. This chip builds in a dual-oscillator to enhance the total
chip performance. The device is suitable for TypeI/II CID cord phone.
1 V2.1
1 page  
Pad Description (Total 92 pads)
Pad No.
24
32
37
Pin No.
(QFP100)
26
36
41
Designation
VDD
AVDD
GND
30 34
31 35
36 40
35 39
RESET
TEST
OSCO
OSCI
34 38
OSCXO
SH67P93
I/O Description
P Digital Power supply
P Analog Power supply
P Ground pin
I Reset pin (internal floating, connection for user)
I Test Pin, internal pull low (no connection for user)
O Low Oscillator output pin (32768Hz crystal or 262K RC)
I Low Oscillator input pin (32768Hz crystal or 262K RC)
O High Oscillator output pin (3.58MHz ceramic or 1.8M RC)
33
38 - 41
42 - 45
54 - 57
58 - 61
62 - 65
66 - 68
69 - 80
81 - 11
46 - 53
19 - 12
20, 21,
23, 22
25
26
29
27
28
37
42 - 45
46 - 49
60 - 63
64 - 67
68 - 71
72 - 74
75 - 76
79 - 88
89 - 1
3 - 13
50 - 51,
54 - 59
21 - 14
22, 23,
25, 24
29
30
33
31
32
OSCXI
I High Oscillator input pin (3.58MHz ceramic or 1.8M RC)
Port A3 - 0
Bit programmable I/O
I/O PortA.0 shared with INT0
PortA.3 had powerful sink capacity to driver LED directly
Bit programmable I/O, Vector interrupt ( INT1 )
Port B.3
For the caller ID application:
Port B.2/FILIN
Port B.1/FILOUT
I/O
PortB.2 is shared with FILIN input pin
PortB.1 is shared with FILOUT output pin
Port B.0/AGCIN
PortB.0 is shared with AGCIN input pin
When PortB0 - 2 is shared, the interrupt input and the pull high resistor
setting for PB0 - 2 is disable
PortC.3 - 0
/Segment50 - 47
I/O
Bit programmable I/O, Vector interrupt ( INT1 )
Segment50 - 47 shared with PortC
PortD.3 - 0
/Segment46 - 43
I/O
Bit programmable I/O, Vector interrupt ( INT1 )
Segment46 - 43 shared with PortD
PortE.3 - 0
/Segment42 - 39
I/O
Bit programmable I/O
Segment42 - 39 shared with PortE
PortF.2 - 0
/Segment38 - 36
I/O
Bit programmable I/O
Segment38 - 36 shared with PortF
Segment35 - 24 O Segment signal for LCD display / scan output port
Segment23 - 1 O Segment signal output for LCD display
COM1 - COM16 O Common signal output for LCD display
C1+, C1-, VP1,
VP2
I Connect with external components of LCD power
TIP I Connected with TIP side & Ring side for twisted pair
RING
I
DTMF
O The output pin of DTMF/FSK Generator
CASTIP
I CAS tone input pin
OPOUT
O Pre-amplifier output
5
5 Page 
SH67P93
Configuration of System Register (Continued)
Address Bit 3
Bit 2
Bit 1
Bit 0 R/W
Remarks
IRQ_PA0: the interrupt flag of the PORTA0
IRQ_FSKIN: the interrupt flag of the FSK CMP
$17
FSKIN_
STAT
IRQ_
FSKTX
IRQ_
FSKIN
IRQ_PA0
IRQ_FSKTX: the interrupt flag of the FSK generator after
R/W
a FSK data is transmitted
FSKIN_STAT: the status bit of FSKIN level
1: the source of FSKIN is high level
0: the source of FSKIN is low level
$18 PACR.3 PACR.2 PACR.1 PACR.0 R/W Set PORTA to be output or input mode
$19 PBCR.3 PBCR.2 PBCR.1 PBCR.0 R/W Set PORTB to be output or input mode
$1A PCCR.3 PCCR.2 PCCR.1 PCCR.0 R/W Set PORTC to be output or input mode
$1B PDCR.3 PDCR.2 PDCR.1 PDCR.0 R/W Set PORTD to be output or input mode
$1C PECR.3 PECR.2 PECR.1 PECR.0 R/W Set PORTE to be output or input mode
$1D - PFCR.2 PFCR.1 PFCR.0 R/W Set PORTF to be output or input mode
$1E PPULL HLM
OXM
OXON
R/W
Bit3: Port pull-High resistor control
Bit2: Heavy load mode
Bit1 CPU clocks select (1: OSCX/0: OSC)
Bit0: Turn on OSCX oscillator
$1F
ROM
BNK3
ROM
BNK2
ROM
BNK1
ROM
BNK0
W ROM bank register
$20
-
RAM
BNK2
RAM
BNK1
RAM
BNK0
W RAM bank register
$21 RDT.3 RDT.2 RDT.1 RDT.0 R/W
$22 RDT.7 RDT.6 RDT.5 RDT.4 R/W
ROM Data table address / data register
$23 RDT.11 RDT.10 RDT.9 RDT.8 R/W
$24 RDT.15 RDT.14 RDT.13 RDT.12 R/W
$25 Reserved
$26
FSK_ON
FSK_
DTMF
TGC_COL TGC_ROW R/W
DTMF/FSK control register
R
$27
-
FSK_MD FSK_PRE FSK_TXEN
R/W
R/W
Bit3: Reserved
Bit2 - 0: FSK control bits
R/W
$28 FSK_D7 FSK_D6 FSK_D5 FSK_D4 R/W High nibble data of FSK Data to be transimitted
$29
FSK_D3/ FSK_D2/ FSK_D1/ FSK_D0/
TGD3 TGD2 TGD1 TGD0
R/W
Low nibble data of FSK Data to be transimitted/
Tone data register
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH67P93.PDF ] | |
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