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PDF NB3N5573 Data sheet ( Hoja de datos )

Número de pieza NB3N5573
Descripción Dual HCSL Clock Generator
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NB3N5573
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL Clock
Generator
Description
The NB3N5573 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 4).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
External Loop Filter is Not Required
HCSL Differential Output or LVDS with Proper Termination
Four Selectable Multipliers of the Input Frequency
Output Enable with Tri−State Outputs
PCIe Gen1, Gen2, Gen3 Jitter Compliant
Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz −109.4 dBc
1 kHz −127.8 dBc
10 kHz −136.2 dBc
100 kHz −138.8 dBc
1 MHz −138.2 dBc
10 MHz −161.4 dBc
20 MHz −163.00 dBc
Typical Period Jitter RMS of 1.5 ps
Operating Range 3.3 V ±10%
Industrial Temperature Range −40°C to +85°C
These are Pb−Free Devices
www.onsemi.com
16
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
5573
ALYWG
1G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VDD
X1/CLK
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
Charge
Pump
BM
VCO
HSCL
Output
HSCL
Output
CLK0
CLK0
CLK1
CLK1
GND
S0
Figure 1. NB3N5573 Simplified Logic Diagram
S1 OE IREF
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 10
1
Publication Order Number:
NB3N5573/D

1 page




NB3N5573 pdf
NB3N5573
Table 7. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
Symbol
Parameter
Conditions (Notes 8 and 9)
Min Typ Max Unit
tjphPCIeG1
tjphPCIeG2
PCIe Gen 1 (Notes 10 and 11)
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Note 10)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Note 10)
10 86 ps (p−p)
0.2
3
ps
(rms)
0.9
3.1
ps
(rms)
tjphPCIeG3 RMS Phase Jitter
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Note 10)
0.2
1
ps
(rms)
QPI & SMI
(100.00 MHz or 133.33 MHz,
4.8 Gb/s, 6.4 Gb/s 12UI) (Note 12)
0.1
0.5
ps
(rms)
tjphQPI_SMI
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Note 12)
0.1
0.3
ps
(rms)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Note 12)
0.07
0.2
ps
(rms)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Applies to all outputs.
9. Guaranteed by design and characterization, not tested in production
10. See http://www.pcisig.com for complete specs
11. Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
12. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
HCSL INTERFACE
NB3N5573 CLK0
CLK0
RL = 33.2 W
RL = 33.2 W
HCSL
Driver
CLK1
RL = 33.2 W
IREF
RL = 33.2 W
CLK2
Zo = 50 W
Zo = 50 W
Zo = 50 W
Zo = 50 W
RL = 49.9 W
RL = 49.9 W
HCSL
Receiver
RL = 49.9 W
RL = 49.9 W
RREF = 475 W
Figure 3. Typical Termination for Output Driver and Device Evaluation
www.onsemi.com
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