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PDF NB3N51032 Data sheet ( Hoja de datos )
| Número de pieza | NB3N51032 | |
| Descripción | Dual HCSL/LVDS Clock Generator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB3N51032
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL/LVDS
Clock Generator
The NB3N51032 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
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25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 10). The NB3N51032 provides selectable
spread options of −0.5% and −0.75% for applications demanding low
Electromagnetic Interference (EMI) as well as optimum performance
with no spread option.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
MARKING
DIAGRAM
16 16
NB3N
1
TSSOP−16
DT SUFFIX
1032
ALYWG
1G
CASE 948F
A = Assembly Location
L = Wafer Lot
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• Four Selectable Multipliers of the Input Frequency
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
• Output Enable with Tri−State Outputs
• PCIe Gen 1, Gen 2, Gen 3 Compliant
• Spread of −0.5%, −0.75% and No Spread
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
• Phase Noise: @ 100 MHz
Offset Noise Power
Applications
• Networking
100 Hz −88 dBc/Hz
• Consumer
1 kHz −118 dBc/Hz
10 kHz −131 dBc/Hz
100 kHz −132 dBc/Hz
1 MHz −144 dBc/Hz
10 MHz −155 dBc/Hz
• Typical Period Jitter RMS of 1.5 ps
• Computing and Peripherals
• Industrial Equipment
• PCIe Clock Generation Gen 1, Gen 2 and Gen 3
• Gigabit Ethernet
• FB DIMM
• Operating Supply Voltage Range 3.3 V ±5%
• Industrial Temperature Range −40°C to +85°C
• Functionally Compatible with IDT557−03,
IDT5V41065, IDT5V41235 with enhanced performance
• These are Pb−Free Devices
End Products
• Switch and Router
• Set Top Box, LCD TV
• Servers, Desktop Computers
• Automated Test Equipment
VDD SS0 SS1
X1/CLK
Spread Spectrum
Circuit
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
Charge
Pump
BN
VCO
HCSL
Output
HCSL
Output
CLK0
CLK0
CLK1
CLK1
VDD = VDDODA = VDDXD
GND = GNDODA = GNDXD
GND
S0 S1
Figure 1. NB3N51032 Simplified Logic Diagram
OE IREF
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 2
1
Publication Order Number:
NB3N51032/D
1 page  
NB3N51032
Table 7. AC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C; Note 9)
Symbol
Characteristic
Min
fCLKIN
fCLKOUT
FNOISE
Clock/Crystal Input Frequency
Output Clock Frequency
Phase−Noise Performance
fCLKOUT = 100 Mhz
@ 100 Hz offset from carrier
@ 1 kHz offset from carrier
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 10 MHz offset from carrier
25
tJITTER
tJIT(F)
fMOD
SSCRED
Period Jitter Peak−to−Peak (Note 10)
Period Jitter RMS (Note 10)
Cycle−Cycle RMS Jitter (Note 11)
Cycle−to−Cycle Peak to Peak Jitter (Note 11)
fCLKOUT = 200 Mhz
fCLKOUT = 200 MHz
fCLKOUT = 200 MHz
fCLKOUT = 200 MHz
Phase RMS Jitter, Integration Range 12 kHz to 20 MHz
Spread Spectrum Modulation Frequency
Spectral Reduction, fCLKOUT of 100 MHz with −0.5% spread, 3rd Harmonic
(Note 12)
30
tSKEW
Eppm
Within Device Output to Output Skew
Frequency Synthesis Error, All Outputs
tSPREAD
Spread Spectruction Transition Time
(Stablization Time After Spread Spectrum Changes)
7
tOE
tDUTY_CYCLE
tR
tF
DtR
DtF
Stabilization
Time
Output Enable/Disable Time (Note 13)
Output Clock Duty Cycle (Measured at cross point)
Output Risetime (Measured from 175 mV to 525 mV, Figure 11)
Output Falltime (Measured from 525 mV to 175 mV, Figure 11)
Output Risetime Variation (Single−Ended)
Output Falltime Variation (Single−Ended)
Stabilization Time From Powerup VDD = 3.3 V
45
175
175
Typ
25
−88
−118
−131
−132
−144
−155
10
1.5
2.0
20
0.5
31.5
−10
0
50
3.0
Max Unit
MHz
200 MHz
dBc/Hz
20 ps
3.0
5.0
35
ps
33 kHz
dB
40 ps
ppm
30 ms
10 ms
55 %
700 ps
700 ps
125 ps
125 ps
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
9. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted
to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 49.9
W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 9. Guaranteed by characterization.
10. Sampled with 10000 cycles.
11. Sampled with 1000 cycles.
12. Spread spectrum clocking enabled.
13. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH.
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5
5 Page 
700 mV
NB3N51032
525 mV
525 mV
0 mV
175 mV
175 mV
tR tF
Figure 11. HCSL Output Parameter Characteristics
ORDERING INFORMATION
Device
Package
Shipping†
NB3N51032DTG
TSSOP−16
(Pb−Free)
96 Units / Rail
NB3N51032DTR2G
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NB3N51032.PDF ] | |
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