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PDF NB4N121K Data sheet ( Hoja de datos )
| Número de pieza | NB4N121K | |
| Descripción | 3.3V Differential 1:21 Differential Fanout Clock Driver | |
| Fabricantes | ON Semiconductor | |
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NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors.
Output drive current at IREF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect IREF to VCC. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
• Additive Phase RMS Jitter: 1 ps Max
• Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• Differential HCSL Output Level (700 mV Peak−to−Peak)
• Pb−Free Packages are Available
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1 52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB4N
121K
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK
Q19
VTCLK
VCC
GND
RREF
Q19
Q20
IREF Q20
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2012 − Rev. 6
1
Publication Order Number:
NB4N121K/D
1 page  
NB4N121K
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +70°C (Note 7)
Symbol
Characteristic
Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPPmin)
tPLH,
tPHL
Propagation Delay to (See Figure 3)
fin = 133 MHz
fin = 166 MHz
fin = 200 MHz
725 900 mV
725 900
725 900
CLK/CLK to Qx/Qx 550 800 950
ps
DtPLH,
DtPHL
tSKEW
Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx
(Note 8) (See Figure 3)
Duty Cycle Skew (Note 9)
Within−Device Skew, 1X Mode Only (Note 10)
Within−Device Skew, 2X Mode (Note 10)
Device−to−Device Skew (Note 10)
100 ps
20 ps
50 ps
80 ps
150 ps
tjit(f)
Vcross
DVcross
tr, tf
Additive RMS Phase RMS (Note 11) fin =133 MHz to 200 MHz
Absolute Crossing Magnitude Voltage
Variation in Magnitude of Vcross
Absolute Magnitude in Output Risetime and Falltime
(From 175 mV to 525 mV)
1 ps
250 550 mV
150 mV
Qx, Qx 175 340 700
ps
Dtr, Dtf
Variation in Magnitude of Risetime and Falltime (Single−Ended)
(See Figure 4)
Qx, Qx
1X
2X
ps
125
150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded
50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X
configuration, connect IREF to VCC. Typical gain is 20 dB.
8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges.
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
10. Skew is measured between outputs under identical transition @ 133 MHz.
11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz
CLK
CLK
Q
tPLH
VINPP = VIH(CLK) − VIL(CLK)
= VIH(CLK) − VIL(CLK)
tPHL
VOUTPP = VOH(Q) − VOL(Q)
= VOH(Q) − VOL(Q)
Q
DtPLH
DtPHL
Figure 3. AC Reference Measurement
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