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부품번호 | RK2918 기능 |
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기능 | High performance processor solution | ||
제조업체 | Rockchip | ||
로고 | |||
RK2918 Datasheet
Rev 1.0
RK2918 Datasheet
Preliminary
Revision 1.0
Jan. 2011
Rockchips Confidential
1
RK2918 Datasheet
Rev 1.0
Figure Index
Fig. 1-1 RK2918 Block Diagram........................................................................ 20
Fig. 2-1 RK2908 Ball Mapping Diagram.............................................................. 24
Fig. 2-2 RK2908 TFBGA512 Package Top View .................................................... 58
Fig. 2-3 RK2908 TFBGA512 Package Side View................................................... 58
Fig. 2-4 RK2908 TFBGA512 Package Bottom View............................................... 59
Fig. 2-5 RK2908 TFBGA512 Package Dimension.................................................. 59
Fig. 4-1 External reference circuit for 24MHz/27MHz oscillators............................. 66
Fig. 4-2 External reference circuit for 32.768KHz oscillator................................... 66
Fig. 4-3 External reference circuit for PLL .......................................................... 67
Fig. 4-4 RK2918 USB OTG/Host2.0 interface reference connection......................... 67
Fig. 4-5 RK2918 reset signals sequence............................................................. 68
Rockchips Confidential
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4페이지 RK2918 Datasheet
Rev 1.0
ARMv7 debug with watchpoint and breakpoint registers and a 32-bit APB slave
interface to a coresight debug system
Four separate power domain to support Internal power switch on/off based on
different application scene(Integer core/ETM&DBG/Neon/L2 Cache)
Maximum frequency can be up to 650MHz@worst case and 1GHz@typical case
1.1.2 Memory Organization
Internal on-chip memory
10KB Boot Rom
16KB internal SRAM for security and non-security access, detailed size is
programmable
4KB internal SRAM shared with Host slave interface (HIF)
2KB internal SRAM shared with NAND controller
External off-chip memory①
DDRIII, DDRII-800, 16/32bits data width, 2 ranks, 1GB(max) address space per
rank
LPDDR-400, 32bits data width, 2 ranks, 1GB(max) address space per rank
Async SRAM/Nor Flash, 8/16bits data width,2banks,1MB(max) address space
per bank
Async NAND Flash(include LBA NAND), 8/16bits data width, 8 banks
Sync DDR NAND Flash, 8bits data width, 8 banks
1.1.3 Internal Memory
Internal Boot Rom
Size : 10KB
Support system boot from the following device :
8bits/16bits Async NAND Flash
SPI0 interface
eMMC interface
Support system code download by the following interface:
USB OTG
UART1
Internal SRAM
Size : 16KB
Support security and non-security access
Security or non-security space is software programmable , used together with
TZMA module
Security space can be 0KB, 4KB, 8KB, 12KB, 16KB continuous size
1.1.4 External Memory or Storage device
Dynamic Memory Interface (DDRIII/DDRII/LPDDR)
Compatible with JEDEC standard DDRIII/DDRII/LPDDR SDRAM
Data rates of up to 800Mbps(400MHz) for DDRII and up to 400Mbps(200MHz)
for LPDDR
Support up to 2 ranks (chip selects), maximum 1GB address space per rank
16bits/32bits data width is software programmable
5 host ports with 64bits AXI bus interface for system access, AXI bus clock
asynchronous with DDR clock
Programmable timing parameters support DDRIII/DDRII/LPDDR SDRAM from
various vendor
Advanced command reordering and scheduling to maximize bus utilization
Low power modes, such as power-down and self-refresh for DDRII/LPDDR
SDRAM; clock stop and deep power-down for LPDDR SDRAM
Programmable ultra-high priority port(port0), typically a CPU port
Compensation for board delays and variable latencies through programmable
pipelines
Embedded dynamic drift detection in the PHY to get dynamic drift compensation
Rockchips Confidential
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RK2918 | High performance processor solution | Rockchip |
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