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PDF AT24C16D Data sheet ( Hoja de datos )
| Número de pieza | AT24C16D | |
| Descripción | I2C-Compatible (2-Wire) Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT24C16D
I2C-Compatible (2-Wire) Serial EEPROM
16-Kbit (2,048 x 8)
DATASHEET
Features
Low Voltage Operation
̶ VCC = 1.7V to 3.6V
Internally Organized as 2,048 x 8 (16K)
I2C-Compatible (2-Wire) Serial Interface
̶ 100kHz Standard Mode, 1.7V to 3.6V
̶ 400kHz Fast Mode, 1.7V to 3.6V
̶ 1MHz Fast Mode Plus (FM+), 2.5V to 3.6V
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
Write Protect Pin for Full Array Hardware Data Protection
Ultra Low Active Current (1mA max) and Standby Current (0.8μA max)
16-byte Page Write Mode
̶ Partial Page Writes Allowed
Random and Sequential Read Modes
Self-timed Write Cycle Within 5ms Maximum
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Green Package Options (Lead-free/Halide-free/RoHS Compliant)
̶ 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP,(1) 5-lead SOT23,
8-ball VFBGA, and 4-ball WLCSP
Die Sale Options: Wafer Form and Tape and Reel Available
Description
The Atmel® AT24C16D provides 16,384 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 2,048 words of 8 bits
each. This device is optimized for use in many industrial and commercial
applications where low power and low voltage operation are essential. The device
is available in space-saving 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN,
8-lead PDIP(1), 5-lead SOT23, 8-ball VFBGA, and 4-ball WLCSP packages. The
entire family of packages operates from 1.7V to 3.6V.
Note: 1. Contact Atmel Sales for the availability of this package.
Atmel-8906C-SEEPROM-AT24C16D-Datasheet_052015
1 page  
3.3 Acknowledge and No-Acknowledge
After every byte of data is received, the receiving device must confirm to the Master that it has successfully
received the data byte by responding with what is known as an Acknowledge (ACK). An ACK is accomplished
by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle followed by the
receiving device responding with a Logic 0 during the entire high period of the ninth clock cycle.
When the AT24C16D is transmitting data to the Master, the Master can indicate that it is done receiving data
and wants to end the operation by sending a Logic 1 response to the AT24C16D instead of an ACK response
during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the Master
sending a Logic 1 during the ninth clock cycle, at which point the AT24C16D will release the SDA line so the
Master can then generate a Stop condition.
The transmitting device, which can be the bus Master or the Serial EEPROM, must release the SDA line at the
falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a Logic 0 to ACK the
previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow
the transmitter to continue sending new data. A timing diagram has been provided in Figure 3-1 to better
illustrate these requirements.
Figure 3-1. Start Condition, Data Transitions, Stop Condition, and Acknowledge
SDA
Must Be
Stable
SDA
Must Be
Stable
Acknowledge Window
SCL
12
SDA
Start
Condition
SDA
Change
Allowed
SDA
Change
Allowed
89
The transmitting device (Master or Slave)
must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the
SDA line low to ACK the previous 8-bit word.
Stop
Condition
Acknowledge
Valid
The receiver (Master or Slave)
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
3.4 Standby Mode
The AT24C16D features a low power standby mode which is enabled when any one of the following occurs:
A valid power-up sequence is performed (see Section 8.5).
A Stop condition is received by the device unless it initiates an internal write cycle (see Section 5.).
At the completion of an internal write cycle (see Section 5.).
An unsuccessful match of the device type identifier or hardware address in the Device Address byte
occurs (see Section 4.1).
The bus Master does not ACK the receipt of data read out from the device; instead it sends a NACK
response. (see Section 6.).
AT24C16D [DATASHEET]
Atmel-8906C-SEEPROM-AT24C16D-Datasheet_052015
5
5 Page 
6. Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write Select
bit in the Device Address word must be a Logic 1. There are three Read operations:
Current Address Read
Random Address Read
Sequential Read
6.1 Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the VCC is maintained to
the part. The address roll-over during read is from the last byte of the last page to the first byte of the first page
of the memory.
A Current Address Read operation will output data according to the location of the internal data word address
counter. This is initiated with a Start condition, followed by a valid Device Address byte with the R/W bit set to
Logic 1. The device will ACK this sequence and the current address data word is serially clocked out on the
SDA line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it
NACKs) during the ninth clock cycle, which will force the device into standby mode. After the NACK response,
the Master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next
sequence.
Figure 6-1. Current Address Read
SCL
12 3 4 567 89 12 345 67 89
SDA
Start
by
Master
Device Address Byte
Data Word (n)
1 0 1 0 A10 A9 A8 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
6.2 Random Read
A Random Read begins in the same way as a Byte Write operation does to load in a new data word address.
This is known as a “dummy write” sequence; however, the Data Byte and the Stop condition of the Byte Write
must be omitted to prevent the part from entering an internal write cycle. Once the Device Address and Word
Address are clocked in and acknowledged by the EEPROM, the bus Master must generate another Start
condition. The bus Master now initiates a Current Address Read by sending a Start condition, followed by a
valid Device Address byte with the R/W bit set to Logic 1. In this second Device Address byte, the bit positions
usually reserved for the most significant bits of the Word Address (bit 3, 2, and 1) are don’t care bits since the
address that will be read from is determined only by what was sent in the dummy write portion of the sequence.
The EEPROM will ACK the Device Address and serially clock out the data word on the SDA line. All types of
Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs) during the ninth
clock cycle, which will force the device into standby mode. After the NACK response, the Master may send a
Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.
AT24C16D [DATASHEET]
Atmel-8906C-SEEPROM-AT24C16D-Datasheet_052015
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AT24C16D.PDF ] | |
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