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CAV25040 데이터시트 PDF




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기능 EEPROM
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CAV25040 데이터시트, 핀배열, 회로
CAV25010, CAV25020,
CAV25040
1-Kb, 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
Description
The CAV25010/20/40 are 1Kb/2Kb/4Kb Serial CMOS
EEPROM devices internally organized as 128x8/256x8/512x8 bits.
They feature a 16byte page write buffer and support the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are a clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD
input may be used to pause any serial communication with the
CAV25010/20/40 device. These devices feature software and
hardware write protection, including partial as well as full array
protection.
Features
Automotive Temperature Grade 1 (40°C to +125°C)
10 MHz SPI Compatible
2.5 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
16byte Page Write Buffer
Selftimed Write Cycle
Hardware and Software Protection
Block Write Protection
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC and TSSOP 8Lead Packages
These Devices are PbFree, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAV25010
CAV25020
CAV25040
SO
VSS
Figure 1. Functional Symbol
http://onsemi.com
SOIC8
V SUFFIX
CASE 751BD
TSSOP8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
SOIC (V), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
January, 2012 Rev. 0
1
Publication Order Number:
CAV25010/D




CAV25040 pdf, 반도체, 판매, 대치품
CAV25010, CAV25020, CAV25040
Pin Description
SI: The serial data input pin accepts opcodes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAV25010/20/40.
CS: The chip select input pin is used to enable/disable the
CAV25010/20/40. When CS is high, the SO output is
tristated (high impedance) and the device is in Standby
Mode (unless an internal write operation is in progress).
Every communication session between host and
CAV25010/20/40 must be preceded by a high to low
transition and concluded with a low to high transition of the
CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
HOLD: The HOLD input pin is used to pause transmission
between host and CAV25010/20/40, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
to VCC, either directly or through a resistor.
CS
Functional Description
The CAV25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0) and
(1,1). The device contains an 8bit instruction register. The
instruction set and associated opcodes are listed in Table 7.
Reading data stored in the CAV25010/20/40 is
accomplished by simply providing the READ command and
an address. Writing to the CAV25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits in
a Status Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAV25010/20/40 will accept any one of the six instruction
opcodes listed in Table 7 and will ignore all other possible
8bit combinations. The communication protocol follows
the timing from Figure 2.
Table 7. INSTRUCTION SET (Note 9)
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 X011
Read Data from Memory
WRITE
0000 X010
Write Data to Memory
9. X = 0 for CAV25010, CAV25020. X = A8 for CAV25040
tCS
tCNH
tCSS
tWH
tWL
tCSH
tCNS
SCK
tSU tH
SI
VALID
IN
HIZ
SO
tRI
tFI
tV
tHO
VALID
OUT
tV
tDIS
Figure 2. Synchronous Data Timing
HIZ
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are nonvolatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become readonly.
http://onsemi.com
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CAV25040 전자부품, 판매, 대치품
CAV25010, CAV25020, CAV25040
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2 and 3 can be written using the WRSR command.
Write Protection
When WP input is low all write operations to the memory
array and Status Register are inhibited. WP going low while
CS is still low will interrupt a write operation. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the Status Register
or memory array. The WP input timing is shown in Figure 8.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OPCODE
SI 0 0 0 0 0 0
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
0 17 65
MSB
Figure 7. WRSR Timing
DATA IN
4 32
10
tWPS
tWPH
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
http://onsemi.com
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