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부품번호 | XE8805 기능 |
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기능 | Sensing Machine Data Acquisition MCU | ||
제조업체 | Semtech | ||
로고 | |||
전체 30 페이지수
XE8805/05A Sensing Machine
Data Acquisition MCU
with Zooming ADC and DACs
XE8805/05A – SX8805R Sensing
Machine – Data Acquisition with 16+10 bit
ZoomingADC™ and buffered DACs
General Description
The XE8805A is a data acquisition ultra low-
power low-voltage system on a chip (SoC) with a
high efficiency microcontroller unit embedded
(MCU), allowing for 1 MIPS at 300uA and 2.4 V,
and multiplying in one clock cycle.
The XE8805A includes a high resolution
acquisition path with the 16+10 bits ZoomingADC
and two buffered DACs.
The XE8805A is available with on chip ROM (the
SX8805) or Multiple-Time-Programmable (MTP)
program memory.
Applications
• Portable, battery operated instruments
• Current loop powered instruments
• Wheatstone bridge interfaces
• Pressure and chemical sensors
• HVAC control
• Metering
• Sports watches, wrist instruments
Key product Features
• Low-power, high resolution ZoomingADC
• 0.5 to 1000 gain with offset cancellation
• up to 16 bits analog to digital converter
• up to 13 inputs multiplexer
• Low-voltage low-power controller operation
• 2 MIPS with 2.4 V to 5.5 V operation
• 300 µA at 1 MIPS over voltage range
• 22 kByte (8 kInstruction) MTP
• 520 Byte RAM data memory
• RC and crystal oscillators
• 5 reset, 22 interrupt, 8 event sources
• 8 bit and 16 bit buffered DACs
• 100 years MTP Flash retention at 55°C
Ordering Information
Product
Temperature range Memory type
XE8805MI028*
-40°C to 85 °C
MTP
XE8805AMI000
-40°C to 85 °C
MTP
XE8805AMI028LF -40°C to 85 °C
MTP
SX8805Rxxx
-40°C to 85 °C**
ROM
*Not for new designs
**Extended temperature range on request
Package
LQFP64
die
LQFP64
Rev 1 January 2006
www.semtech.com
XE8805/05A
1.1 Top schematic
1.1.1 General description
The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the
Coolrisc816® CPU core. This core includes an 8x8 multiplier and 16 internal registers.
The bus controller generates all control signals for access to all data registers other than the CPU internal
registers.
The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained
in its control registers. Possible reset sources are the power-on-reset (POR), the external pin RESET, the
watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low
power modes are implemented.
The clock generation and power management block sets up the clock signals and generates internal supplies for
different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal
oscillator (XTAL) or an external clock source (given on the OSCIN pin).
The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8
low power data registers. If power consumption is important for the application, the variables that need to be
accessed very often should be stored in these registers rather than in the RAM.
The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows
masking of the interrupt sources and it flags which interrupt source is active.
Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e.
the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the
event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the interrupt
sources and it flags which interrupt source is active.
The Port B is an 8 bit parallel IO port with analog capabilities. The URST, UART, and PWM block also make use of
this port.
The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. Flash and ROM
versions have both 8k instruction memory. The data memory of this product is 512 byte SRAM.
The Acquisition Chain is a high resolution acquisition path with the 16+10 bit fully differential ZoomingADC™. The
VMULT (voltage multiplier) powers a part of the Acquisition Chain.
The signal D/A (DAS) is a 16 bit D/A based on sigma-delta modulation. It includes a stand-alone amplifier that can
be used for analog output filtering.
The bias D/A (DAB) is an 8 bit low frequency D/A. It includes a stand-alone amplifier that is used to drive large
currents. It can be used to bias a sensor.
The Port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input
external clocks for the timer/counter/PWM block.
The Port C is a general purpose 8 bit parallel I/O port.
The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to
simplify the software implementation of a synchronous serial link.
© Semtech 2006
www.semtech.com
1-2
4페이지 XE8805/05A
1.2.2 LQFP-64
The XE8805/05A is delivered in a LQFP-64 package. The pin map is given below.
VPP/TEST
NC
AC_R(3)
AC_R(2)
AC_A(7)
AC_A(6)
AC_A(5)
AC_A(4)
AC_A(3)
AC_A(2)
AC_A(1)
AC_A(0)
AC_R(1)
AC_A(0)
NC
NC
35
40
45
PC(7)
15 PC(6)
PC(5)
PC(4)
PC(3)
PC(2)
10 PC(1)
PC(0)
PA(7)
PA(6)
PA(5)
5 PA(4)
PA(3)
PA(2)
PA(1)
1 PA(0)
Package pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
© Semtech 2006
name
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PC(0)
PC(1)
PC(2)
PC(3)
PC(4)
PC(5)
PC(6)
PC(7)
PB(0)
PB(1)
PB(2)
PB(3)
Figure 1-3. LQFP-64 pin map
Package pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
name
VPP/TEST
NC
AC_R(3)
AC_R(2)
AC_A(7)
AC_A(6)
AC_A(5)
AC_A(4)
AC_A(3)
AC_A(2)
AC_A(1)
AC_A(0)
AC_R(1)
AC_R(0)
NC
NC
NC
NC
DAS_OUT
DAS_AI_P
1-5
www.semtech.com
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