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PDF PH1730AL Data sheet ( Hoja de datos )
| Número de pieza | PH1730AL | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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PH1730AL
N-channel TrenchMOS logic level FET
Rev. 03 — 12 January 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing and consumer applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Consumer applications
Desktop Voltage Regulator Module
(VRM)
Notebook Voltage Regulator Module
(VRM)
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
- - 30 V
ID drain current
Tmb = 25 °C; VGS = 10 V;
[1] -
-
100 A
see Figure 1 and 3
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
- - 109 W
Dynamic characteristics
QGD
gate-drain charge
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
and 15
- 8.7 - nC
QG(tot) total gate charge
Static characteristics
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
- 36.2 - nC
RDSon
drain-source
VGS = 10 V; ID = 15 A;
on-state resistance Tj = 25 °C
- 1.29 1.7 mΩ
[1] Continuous current is limited by package.
1 page  
NXP Semiconductors
PH1730AL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter
Static characteristics
V(BR)DSS drain-source
breakdown voltage
VGS(th)
gate-source threshold
voltage
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
RG gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
QGS(th)
QGS(th-pl)
QGD
VGS(pl)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
Conditions
ID = 20 A; VGS = 0 V; Tj = 25 °C; tav = 100 ns
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11 and 12
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 12
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 12
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 13
VGS = 10 V; ID = 15 A; Tj = 25 °C
f = 1 MHz
ID = 10 A; VDS = 12 V; VGS = 10 V;
see Figure 14 and 15
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14 and 15
VDS = 12 V; see Figure 14 and 15
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
PH1730AL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 12 January 2010
Min Typ Max Unit
35 - - V
30 - - V
27 - - V
1.3 1.7 2.15 V
0.65 - - V
- - 2.45 V
- - 1 µA
- - 100 µA
- - 100 nA
- - 100 nA
- 1.75 2.09 mΩ
- - 2.8 mΩ
-
1.29 1.7
mΩ
-
0.77 1.5
Ω
- 77.9 - nC
- 70 - nC
- 36.2 - nC
- 11.6 - nC
- 8 - nC
- 3.6 - nC
- 8.7 - nC
- 2.34 - V
- 5057 - pF
- 1082 - pF
- 398 - pF
- 46 - ns
- 72 - ns
- 76 - ns
- 34 - ns
© NXP B.V. 2010. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
PH1730AL
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID
Release date Data sheet status
PH1730AL_3
Modifications:
20100112
Product data sheet
• Various changes to content.
PH1730AL_2
20090121
Product data sheet
PH1730AL_1
20080911
Preliminary data sheet
Change notice
-
-
-
Supersedes
PH1730AL_2
PH1730AL_1
-
PH1730AL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 12 January 2010
© NXP B.V. 2010. All rights reserved.
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