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NVMFD5485NLT1G 데이터시트 PDF




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기능 Power MOSFET ( Transistor )
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NVMFD5485NLT1G 데이터시트, 핀배열, 회로
NVMFD5485NL
Power MOSFET
60 V, 44 mW, 20 A, Dual N−Channel
Features
Small Footprint (5x6 mm) for Compact Designs
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
175°C Operating Temperature
NVMFD5485NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
This is a Pb−Free Device
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJC
(Notes 1, 2, 4)
Power Dissipation
RqJC (Notes 1, 2)
Steady
State
TC = 25°C
TC = 100°C
TC = 25°C
TC = 100°C
Continuous Drain
Current RqJA
(Notes 1, 3 & 4)
Power Dissipation
RqJA (Notes 1 & 3)
Steady
State
TA = 25°C
TA = 100°C
TA = 25°C
TA = 100°C
Pulsed Drain Current TA = 25°C, tp = 10 ms
Operating Junction and Storage Temperature
VDSS
VGS
ID
PD
ID
PD
IDM
TJ, Tstg
60
"20
19.5
13.8
38.5
19.2
5.3
3.8
2.9
1.4
113
−55 to
175
V
V
A
W
A
W
A
°C
Source Current (Body Diode)
IS 37 A
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL(pk) = 25 A, L = 0.1 mH, RG = 25 W)
EAS 31 mJ
Lead Temperature for Soldering Purposes
(1/8from case for 10 s)
TL 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol Value Unit
Junction−to−Case − Steady State (Note 2)
RqJC
3.9 °C/W
Junction−to−Ambient − Steady State (Note 3) RqJA
52
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted to an ideal (infinite) heat sink.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second are higher but are dependent
on pulse duration and duty cycle.
www.onsemi.com
V(BR)DSS
60 V
RDS(on) MAX
44 mW @ 10 V
60 mW @ 4.5 V
ID MAX
20 A
Dual N−Channel
D1
D2
G1 G2
S1 S2
MARKING DIAGRAM
1
DFN8 5x6
(SO8FL)
CASE 506BT
D1 D1
S1 D1
G1 XXXXXX D1
S2 AYWZZ D2
G2 D2
D2 D2
XXXXXX = 5485NL
XXXXXX = (NVMFD5485NL) or
XXXXXX = 5485LW
XXXXXX = (NVMFD5485NLWF)
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
ORDERING INFORMATION
Device
Package Shipping
NVMFD5485NLT1G
DFN8
1500/
(Pb−Free) Tape & Reel
NVMFD5485NLT3G
DFN8
5000/
(Pb−Free) Tape & Reel
NVMFD5485NLWFT1G DFN8
1500/
(Pb−Free) Tape & Reel
NVMFD5485NLWFT3G DFN8
5000/
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 3
1
Publication Order Number:
NVMFD5485NL/D




NVMFD5485NLT1G pdf, 반도체, 판매, 대치품
NVMFD5485NL
TYPICAL CHARACTERISTICS
1000
900
800
700
600
500
400
300
200
100
0
0
TJ = 25°C
VGS = 0 V
Ciss
Coss
Crss
10 20 30 40 50
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
60
12
QT
10
8 TJ = 25°C
6
4 Qgs
Qgd
2
VDD = 48 V
ID = 10 A
0
0 2 4 6 8 10 12 14 16 18 20
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
100
10
VDD = 48 V
VGS = 4.5 V
ID = 10 A
td(off)
tr
tf
td(on)
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
10
9 TJ = 25°C
8 VGS = 0 V
7
6
5
4
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
TC = 25°C
VGS = 10 V
Single Pulse
10 ms
100 ms
1 ms
10 ms
dc
1
0.1
0.01
0.1
RDS(on) Limit
Thermal Limit
Package Limit
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
www.onsemi.com
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