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PDF STD110N02R Data sheet ( Hoja de datos )
| Número de pieza | STD110N02R | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTD110N02R, STD110N02R
Power MOSFET
24 V, 110 A, N−Channel DPAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low RDS(on) to Minimize Conduction Loss
• Low Ciss to Minimize Driver Loss
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C, Chip
− Continuous @ TC = 25°C
Limited by Package
− Continuous @ TA = 25°C
Limited by Wires
− Single Pulse (tp = 10 ms)
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
RqJC
PD
ID
ID
ID
ID
RqJA
PD
ID
RqJA
PD
ID
TJ, Tstg
24
±20
1.35
110
110
110
32
110
52
2.88
17.5
100
1.5
12.5
−55 to
175
V
V
°C/W
W
A
A
A
A
°C/W
W
A
°C/W
W
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL = 15.5 Apk, L = 1.0 mH, RG = 25 W)
EAS 120 mJ
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
TL 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
V(BR)DSS
24 V
RDS(on) TYP
4.1 mW @ 10 V
ID MAX
110 A
D
N−Channel
G
S
4
12
3
DPAK
CASE 369AA
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
T110N2
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 11
1
Publication Order Number:
NTD110N02R/D
1 page  
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01 Single Pulse
0.00001
0.0001
NTD110N02R, STD110N02R
0.001
0.01
t, TIME (s)
Figure 12. Thermal Response
0.1
1.0 10
ORDERING INFORMATION
Device
Package
Shipping†
NTD110N02RT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
STD110N02RT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet STD110N02R.PDF ] | |
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